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Section 17 I
This LSI has a four-channel I
2
The I
C bus interface conforms to and provides a subset of the Philips I
interface functions. The register configuration that controls the I
Philips configuration, however.
Figure 17.1 shows a block diagram of the I
Figure 17.2 shows an example of I/O pin connections to external circuits.
17.1
Features
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of the SCL is monitored per bit, and the timing is synchronized
automatically
If transfer is not ready, set the SCL to low until preparations are completed.
• Multiple slave addresses can be set
Maximum three types of slave addresses can be set independently. Using the slave address
mask register enables more slave addresses to be set.
• Six interrupt sources
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
• Direct bus drive
SCL and SDA pins function as NMOS open-drain outputs.
IFIIC50A_010020030300
2
C Bus Interface 3 (IIC3)
2
C bus interface 3 (IIC3).
2
C bus interface 3.
2
C bus (inter-IC bus)
2
C bus differs partly from the
Rev. 1.00, 09/03, page 475 of 704
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