Renesas H8S/2437 Hardware Manual page 416

Bit Bit Name
3 VFEDG
2 PREQF
1 IHI
0 IVI
Rev. 1.00, 09/03, page 378 of 704
Initial Value R/W
0 R/(W)*
0 R/(W)*
*
2
R
*
2
R
Description
1
VFBACKI Edge
Detects a rising edge on the VFBACKI pin in
channel 0.
This bit is reserved in channel 1. This bit is always
read as 0 and cannot be modified.
0: [Clearing condition]
When 0 is written to VFEDG after reading VFEDG =
1
1: [Setting condition]
When a rising edge is detected on the VFBACKI pin
1
Pre-Equalization Flag
Detects the occurrence of a 2fH modification
condition for the IHI signal. The generation of a
falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH
modification condition. For details, see section
13.4.4, 2fH Modification of IHI Signal.
0: [Clearing condition]
When 0 is written to PREQF after reading PREQF =
1
1: [Setting condition]
When a 2fH modification condition for the IHI signal
is detected
IHI Signal Level
Indicates the current level of the IHI signal. A signal
source and phase inversion are selected for the IHI
signal depends on the contents of TCONRI. Read
this bit to determine whether the input signal is
positive or negative, then hold the IHI signal at
positive phase by modifying TCONRI.
0: The IHI signal is low
1: The IHI signal is high
IVI Signal Level
Indicates the current level of the IVI signal. A signal
source and phase inversion are selected for the IVI
signal depends on the contents of TCONRI. Read
this bit to determine whether the input signal is
positive or negative, then hold the IVI signal at
positive phase by modifying TCONRI.
0: The IVI signal is low
1: The IVI signal is high