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20.2
Input/Output Pins
Table 20.2 shows the flash memory pin configuration.
Table 20.2 Pin Configuration
Pin Name
I/O
RES
Input
FWE
Input
MD2
Input
MD1
Input
MD0
Input
TxD1
Output
RxD1
Input
20.3
Register Descriptions
The registers/parameters which control flash memory are shown below. To access these registers,
the FLSHE bit in SYSCR must be set to 1. For details on SYSCR, see section 3.2.2, System
Control Register (SYSCR).
• Flash code control/status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass/fail result (DPFR)
• Flash pass/fail result (FPFR)
• Flash multipurpose address area (FMPAR)
• Flash multipurpose data destination area (FMPDR)
• Flash erase block select (FEBS)
• Flash program/erase frequency control (FPEFEQ)
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 20.3.
Function
Reset
Flash memory programming/erasing enable pin
Sets operating mode of this LSI
Sets operating mode of this LSI
Sets operating mode of this LSI
Serial transmit data output (used in boot mode)
Serial receive data input (used in boot mode)
Rev. 1.00, 09/03, page 533 of 704
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