Timer Control Register (Tcr) - Renesas H8S/2437 Hardware Manual

flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a
TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare-
match B signal and the settings of the OS3 and OS2 bits in TCSR. TCORB is initialized to H'FF.
11.3.4

Timer Control Register (TCR)

TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
Bit Bit Name Initial Value R/W Description
7 CMIEB 0
6 CMIEA 0
5 OVIE 0
4 CCLR1 0
3 CCLR0 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
Rev. 1.00, 09/03, page 274 of 704
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is enabled
or disabled when the OVF flag in TCSR is set to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
R/W Counter Clear 1, 0
R/W Select the method by which TCNT is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
R/W Clock Select 2 to 0
R/W Select the clock input to TCNT and count condition,
together with the ICKS1 and ICKS0 bits in TECR (ICKS1_1
R/W
and ICKS0_1 in channel 1, and ICKS1_0 and ICKS0_0 in
channel 0). For details, see table 11.2.