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• P66/TxD2/D6
The pin function is switched as shown below according to the combination of the operating
mode, the TE bit in SCR of the SCI_2, and the P66DDR bit.
• Extended Mode (EXPE = 1)
Bus width*
TE
P66DDR
Pin function
Note:
* When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1, bus width is 8 bits,
if any are cleared to 0, bus width is 16 bits.
• Single-Chip Mode (EXPE = 0)
TE
P66DDR
Pin function
• P65/SCK2/D5
The pin function is switched as shown below according to the combination of the operating
mode, the C/A bit in SMR of the SCI_2, the CKE0 and CKE1 bits in SCR, and the P65DDR
bit.
• Extended Mode (EXPE = 1)
Bus width*
CKE1
C/A
CKE0
P65DDR
Pin function
Note:
* When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1, bus width is 8 bits,
if any are cleared to 0, bus width is 16 bits.
Normal Extended Mode (ADMXE = 0)
16-bit
D6 I/O pin
0
0
P66 input pin
Normal Extended Mode (ADMXE = 0)
16-bit
D5 I/O pin
8-bit
Single-chip operation
1
P66 output pin
8-bit
Single-chip operation
Multiplex Extended Mode
(ADMXE = 1)
Single-chip operation
1
TxD2 output pin
Multiplex Extended Mode
(ADMXE = 1)
Single-chip operation
Rev. 1.00, 09/03, page 177 of 704
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