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Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. Not available in this LSI. Becomes reserved for system use.
4. For details on internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 15,
Watchdog Timer (WDT).
The interrupt control mode is 0 immediately after reset.
4.3.1
Reset exception handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception-handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
Rev. 1.00, 09/03, page 59 of 704
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