Figure 6.15 Bus Timing For 8-Bit, 3-State Data Access Space (With Address Wait) - Renesas H8S/2437 Hardware Manual

8-Bit, 3-State Data Access Space:
Figure 6.15 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (AD15 to AD8) of the address bus and the data bus are used. Wait states
can be inserted.
T
AD15 to AD8
Note: n = 1 to 3

Figure 6.15 Bus Timing for 8-Bit, 3-State Data Access Space (With Address Wait)

Read Cycle
Data
Address
T T T T
1 AW 2 3
Address
Address
T T T T
4 DSW 5
1
Data Address
Write Cycle
Data
T T T
AW 2 3 4
Data
Rev. 1.00, 09/03, page 115 of 704
T T
DSW 5