Usage Notes; Conflict Between Frc Write And Clear; Figure 10.17 Frc Write-Clear Conflict - Renesas H8S/2437 Hardware Manual

10.7

Usage Notes

10.7.1

Conflict between FRC Write and Clear

If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 10.17 shows the timing for this type of
conflict.
Write cycle of FRC
T 1
φ
Address FRC address
Internal write
signal
Counter clear
signal
FRC

Figure 10.17 FRC Write-Clear Conflict

T 2
N H'0000
Rev. 1.00, 09/03, page 261 of 704