Timer Interrupt Enable Register (Tier) - Renesas H8S/2437 Hardware Manual

12.3.4

Timer Interrupt Enable Register (TIER)

TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of
three TIER registers, one for each channel.
Bit Bit Name Initial Value
7 TTGE 0

6 1
5 TCIEU 0
4 TCIEV 0
3 TGIED 0
2 TGIEC 0
R/W Description
R/W A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
R Reserved
This bit is always read as 1 and cannot be modified.
R/W Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2. In channel 0, bit 5 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
R/W Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
R/W TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in channel
0. In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD disabled
1: Interrupt requests (TGID) by TGFD enabled
R/W TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in channel
0. In channels 1 and 2, bit 2 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC disabled
1: Interrupt requests (TGIC) by TGFC enabled
Rev. 1.00, 09/03, page 319 of 704