AD15 to AD8
AD7 to AD0
Note:
n = 1 to 3
Figure 6.19 Bus Timing for 16-Bit, 2-State Data Access Space (4)
(Odd Byte Access, without Address Wait)
Read Cycle
Address
Data
T
T
T
T
1
2
3
4
Address
Address
Data
Write Cycle
Address
Data
T
T
T
T
1
2
3
4
Address
Address
Data
Rev. 1.00, 09/03, page 119 of 704