Table of Contents
Advertisement
2
C Bus Interface 3 (IIC3) ............................................................... 475
17.1 Features .............................................................................................................................475
17.2 Input/Output Pins ..............................................................................................................478
17.3 Register Descriptions ........................................................................................................478
2
17.3.1 I
C Bus Control Register A (ICCRA) ..................................................................479
2
17.3.2 I
C Bus Control Register B (ICCRB)...................................................................480
2
17.3.3 I
C Bus Mode Register (ICMR) ...........................................................................482
2
17.3.4 I
C Bus Interrupt Enable Register (ICIER) ..........................................................483
2
17.3.5 I
C Bus Status Register (ICSR)............................................................................485
17.3.6 Slave Address Register (SAR) .............................................................................487
17.3.7 Slave Address Register A (SARA) ......................................................................487
17.3.8 Slave Address Register B (SARB).......................................................................488
17.3.9 Slave Address Mask Register (SAMR)................................................................488
2
17.3.10 I
C Bus Status Register A (ICSRA) .....................................................................489
2
17.3.11 I
C Bus Transmit Data Register (ICDRT)............................................................489
2
17.3.12 I
C Bus Receive Data Register (ICDRR) .............................................................489
2
17.3.13 I
C Bus Shift Register (ICDRS) ...........................................................................490
17.4 Operation...........................................................................................................................491
2
17.4.1 I
C Bus Format.....................................................................................................491
17.4.2 Master Transmit Operation ..................................................................................492
17.4.3 Master Receive Operation....................................................................................494
17.4.4 Slave Transmit Operation ....................................................................................496
17.4.5 Slave Receive Operation......................................................................................498
17.4.6 Noise Canceler .....................................................................................................500
17.4.7 Example of Use....................................................................................................500
17.5 Interrupt Requests .............................................................................................................505
17.6 Bit Synchronous Circuit....................................................................................................506
Section 18 A/D Converter................................................................................. 507
18.1 Features .............................................................................................................................507
18.2 Input/Output Pins ..............................................................................................................509
18.3 Register Descriptions ........................................................................................................510
18.3.1 A/D Data Registers A to H (ADDRA to ADDRH)..............................................510
18.3.2 A/D Control/Status Register (ADCSR) ...............................................................511
18.3.3 A/D Control Register (ADCR) ............................................................................513
18.4 Operation...........................................................................................................................514
18.4.1 Single Mode.........................................................................................................514
18.4.2 Scan Mode ...........................................................................................................514
18.4.3 Input Sampling and A/D Conversion Time..........................................................515
18.4.4 External Trigger Input Timing .............................................................................516
18.5 Interrupt Source.................................................................................................................517
18.6 A/D Conversion Accuracy Definitions .............................................................................518
18.7 Usage Notes ......................................................................................................................520
Rev.1.00, 09/03, page xix of xxxviii
Advertisement
Table of Contents
