Figure 6.6 Bus Timing For 8-Bit, 3-State Access Space - Renesas H8S/2437 Hardware Manual

8-Bit, 3-State Access Space:
Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
Address bus
D15 to D8
Read
D7 to D0
Write
D15 to D8
Note: n = 1 to 3

Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space

Rev. 1.00, 09/03, page 106 of 704
Bus cycle
T T
1 2
Valid
T
3
Valid
Invalid