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Type
Symbol
WAIT
Bus control
RD
HWR
LWR
AS
CS3 to CS1
AH
Interrupts
NMI
IRQ7 to IRQ0 76 to 73
ExIRQ7 to
ExIRQ0
ETRST*
On-chip
emulator
ETMS
ETDO
ETDI
ETCK
8-bit PWM
PW7 to PW0
timer (PWM)
ExPW7 to
ExPW0
Rev. 1.00, 09/03, page 10 of 704
Pin No.
I/O
22
Input
18
Output This pin is low when the external address space
19
Output This pin is low when the external address space
14
Output This pin is low when the external address space
20
Output This pin is low when address output on the
91, 15, 17 Output Chip select signals for areas 3 to 1.
20
Output Address latch signal for address/data multiplex
27
Input
Input
52 to 49
70 to 67
1 to 4
2
39
Input
35
Input
40
Output
38
Input
36
Input
116, 117,
Output Pulse output pins for the PWM timer.
119, 124
97, 98,
48, 47,
76 to 73
Name and Function
Requests insertion of a wait state in the bus
cycle when accessing an external 3-state
address space.
is being read.
is to be written to, and the upper half of the data
bus is enabled.
is to be written to, and the lower half of the data
bus is enabled.
address bus is valid.
bus.
Nonmaskable interrupt request input pin
These pins request a maskable interrupt.
Selectable to which pin of IRQn or ExIRQn to
input IRQ7 to IRQ0 interrupts.
Interface pins for the on-chip emulator.
Reset by holding the ETRST pin to low when
activating the H-UDI. At this time, the ETRST pin
should be held low for 20 clocks of ETCK. For
details, see section 24, Electrical
Characteristics. Then, to activate the H-UDI, the
ETRST pin should be set to 1 and desired
values should be set to the ETCK, ETMS, and
ETDI pins. When in the normal operation without
activating the H-UDI, the ETRST, ETCK, ETMS,
and ETDI pins should be set to 1 or high-
impedance. Since these pins are internally
pulled up, care should be taken in the standby
state.
Selectable from which pin of PWn or ExPWn to
output PW5 to PW0.
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