Figure 12.42 Tgi Interrupt Timing (Input Capture); Figure 12.43 Tciv Interrupt Setting Timing - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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TGF Flag Setting Timing in Case of Input Capture:
Figure 12.42 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and
TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
TGR
TGF flag
TGI interrupt
TCFV Flag/TCFU Flag Setting Timing:
Figure 12.43 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and
TCIV interrupt request signal timing. Figure 12.44 shows the timing for setting of the TCFU flag
in TSR by underflow occurrence, and TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
N

Figure 12.42 TGI Interrupt Timing (Input Capture)

H'FFFF

Figure 12.43 TCIV Interrupt Setting Timing

N
H'0000
Rev. 1.00, 09/03, page 355 of 704

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