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Notes: 1. Only 0 can be written, to clear the flag.
2. The initial value is undefined since it depends on the pin state.
13.3.5
Timer Extended Control Register (TECR)
TECR selects the HSYNCO and VSYNCO output signals and the count clock source for the
TMR0 and TMR1.
Bit
Bit Name
7
VS0
6
HS2
5
HS1
4
HS0
3
ICKS1_1
2
ICKS0_1
1
ICKS1_0
0
ICKS0_0
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Vertical Synchronization Signal Output Selection
Selects the signal output from the VSYNCO with the
setting of the VOINV bit in TCONRO. See table 13.4.
Horizontal Synchronization Signal Output Select 2 to
0
Select the signal output from the HSYNCO with the
settings of the HOINV bit in TCONRO. See table
13.3.
Internal Clock Source Select (Channel 1)
Select the clock input to the timer counter (TCNT) for
the TMR0_1 and TMR1_1 and count condition with
the settings of the CKS2 to CKS0 bits in the timer
control register 1 (TCR_1). For details, see section
11.3.4, Timer Control Register (TCR).
Internal Clock Source Select (Channel 0)
Select the clock input to the timer counter (TCNT) for
the TMR0_0 and TMR1_0 and count condition with
the settings of the CKS2 to CKS0 bits in the timer
control register 0 (TCR_0). For details, see section
11.3.4, Timer Control Register (TCR).
Rev. 1.00, 09/03, page 379 of 704
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