Table 12.8 Md3 To Md0 - Renesas H8S/2437 Hardware Manual

Bit Bit Name Initial Value
4 BFA 0
3 MD3 0
2 MD2 0
1 MD1 0
0 MD0 0

Table 12.8 MD3 to MD0

Bit 3 Bit 2
1 2
MD3* MD2*
0 0
1
×
1
[Legend] x: Don't care
Notes: 1. MD3 is a reserved bit. The write value should always be 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to the MD2 bit.
R/W Description
R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated. In
channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
R/W Modes 3 to 0
R/W Set the timer operating mode.
R/W MD3 is a reserved bit. The write value should always be
0. See table 12.8 for details.
R/W
Bit 1 Bit 0
MD1 MD0
0 0
1
1 0
1
0 0
1
1 0
1
× ×
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
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Rev. 1.00, 09/03, page 309 of 704