Edge Sense Register (Sedgr) - Renesas H8S/2437 Hardware Manual

13.3.4

Edge Sense Register (SEDGR)

SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH
modification, and determines the phase of the IVI and IHI signals.
Bit Bit Name
7 VEDG
6 HEDG
5 CEDG
4 HFEDG
Initial Value R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
Description
1
VSYNCI Edge
Detects a rising edge on the VSYNCI pin.
0: [Clearing condition]
When 0 is written to VEDG after reading VEDG = 1
1: [Setting condition]
When a rising edge is detected on the VSYNCI pin
1
HSYNCI Edge
Detects a rising edge on the HSYNCI pin.
0: [Clearing condition]
When 0 is written to HEDG after reading HEDG = 1
1: [Setting condition]
When a rising edge is detected on the HSYNCI pin
1
CSYNCI Edge
Detects a rising edge on the CSYNCI pin.
0: [Clearing condition]
When 0 is written to CEDG after reading CEDG = 1
1: [Setting condition]
When a rising edge is detected on the CSYNCI pin
1
HFBACKI Edge
Detects a rising edge on the HFBACKI pin in
channel 0.
This bit is reserved in channel 1. This bit is always
read as 0 and cannot be modified.
0: [Clearing condition]
When 0 is written to HFEDG after reading HFEDG =
1
1: [Setting condition]
When a rising edge is detected on the HFBACKI pin
Rev. 1.00, 09/03, page 377 of 704