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5.7
Usage Notes
5.7.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to mask interrupts, the masking becomes effective after
execution of the instruction.
When an interrupt enable bit is cleared by an instruction such as BCLR or MOV, if an interrupt is
generated during execution of the instruction, the interrupt concerned will still be enabled on
completion of the instruction, and so interrupt exception handling for that interrupt will be
executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU's
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
φ
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.6 Contention between Interrupt Generation and Disabling
Rev. 1.00, 09/03, page 88 of 704
TIER_0 write cycle by CPU
TIER_0 address
TCIV exception handling
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