Table of Contents
Advertisement
Bit
Bit Name Initial Value R/W
5
TME
0
4
0
3
RST/NMI 0
2
CKS2
0
1
CKS1
0
0
CKS0
0
Note:
* Only 0 can be written, to clear the flag.
Description
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
R/W
Reserved
The initial value should not be changed.
R/W
Reset or NMI
Selects whether an internal reset or an NMI interrupt is
requested when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
R/W
Clock Select 2 to 0
R/W
Select the clock source to be input to TCNT. The
overflow cycle for φ = 20 MHz is enclosed in
R/W
parentheses.
000: φ/2 (cycle: 25.6 µs)
001: φ/64 (cycle: 819.2 µs)
010: φ/128 (cycle: 1.6 ms)
011: φ/512 (cycle: 6.5 ms)
100: φ/2048 (cycle: 26.2 ms)
101: φ/8192 (cycle: 104.8 ms)
110: φ/32768 (cycle: 419.4 ms)
111: φ/131072 (cycle: 1.67 s)
Rev. 1.00, 09/03, page 419 of 704
Advertisement
Table of Contents
