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TPU channel
0 setting
MD3 to MD0
IOB3 to IOB0
B'0000
B'0100
B'1xxx
CCLR2 to
CCLR0
Output
function
[Legend]
x: Don't care
Note:
* When TIOCB0S = 0, MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx, this pin
functions as the TIOCB0 input pin.
• P20/TIOCA0/A8/AD8
When the TIOCA0S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCA0 pin.
According to operating modes, the TPU channel 0 settings by the MD3 to MD0 bits in
TMDR_0, the IOA3 to IOA0 bits in TIORH_0, and the CCLR2 to CCLR0 bits in TCR_0, and
the combination of the TIOCA0S bit and the P20DDR bit, pin functions change as follows.
• Extended Mode (EXPE = 1)
Normal Extended Mode (ADMXE = 0)
P20DDR
Pin function
P20 input pin
• Single-Chip Mode (EXPE = 0)
TIOCA0S
TPU channel
0 setting
P20DDR
Pin function
P20 input pin
(2)
(1)
B'0000
B'0001 to B'0011
B'0101 to B'0111
Output compare
output
0
A8 output pin
0
Table below (2)
0
1
P20 output pin
1
TIOCA0 input pin*
(2)
(2)
B'0010
B'xx00
Multiplex Extended Mode (ADMXE = 1)
1
1
TIOCA0 input pin*
Table below (1)
TIOCA0 output
pin
Rev. 1.00, 09/03, page 153 of 704
(1)
B'0011
Other than B'xx00
Other than
B'10
PWM
mode 2
output
AD8 I/O pin
1
0
P20 input pin
P20 output pin
(2)
B'10
1
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