Operation; C Bus Format; Figure 17.3 I 2 C Bus Formats; Figure 17.4 I 2 C Bus Timing - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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17.4

Operation

2
17.4.1
I

C Bus Format

Figure 17.3 shows the I
following a start condition always consists of 8 bits.
2
(a) I
C bus format
S
SLA
R/
1
7
1
1
2
(b) I
C bus format (start condition retransmission)
S
SLA
R/
1
7
1
1
SDA
SCL
S
2
C bus formats. Figure 17.4 shows the I
A
DATA
A
1
n
1
A
DATA
1
n1
m1
Figure 17.3 I
1-7
8
9
SLA
R/
A
Figure 17.4 I
2
A/
P
1
1
m
A/
S
SLA
R/
1
1
7
1
Upper row: Transfer bit count (n1, n2 = 1 to 8)
Lower row: Transfer frame count (m1, m2 ≥ 1)
2
C Bus Formats
1-7
8
9
DATA
A
2
C Bus Timing
C bus timing. The first frame
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m ≥ 1)
A
DATA
1
1
n2
m2
1-7
8
9
DATA
A
Rev. 1.00, 09/03, page 491 of 704
A/
P
1
1
P

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