φ
t
AD
A15 to A0,
to
t
CSD
(Read)
t
AS
D15 to D0
(Read)
,
(Write)
D15 to D0
(Write)
Figure 24.9 Basic Bus Timing/3-State Access
T 1
T 2
t
AS
t
ASD
t
RSD1
t
ACC4
t
ACC5
t
WRD1
t
t
WDD
WDS
T 3
t
AH
t
ASD
t
RDS
t
WRD2
t
AH
t
WSW2
t
WDH
Rev. 1.00, 09/03, page 679 of 704
t
RSD2
t
RDH