Table of Contents
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This LSI is a microcomputer (MCU) made up of the H8S/2600 CPU with Renesas Technology-
original architecture as its core, and the peripheral functions required to configure a system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space. The instruction set of the H8S/2600 CPU maintains upward
compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition
from the H8/300, H8/300L, or H8/300H to the H8S/2600 CPU.
This LSI is equipped with the flash memory, RAM, two kinds of PWM timers (PWM and
PWMX), a 16-bit free-running timer (FRT), an 8-bit timer (TMR), a 16-bit timer pulse unit (TPU),
a watchdog timer (WDT), a timer connection, a serial communication interface (SCI), an I
interface 3 (IIC3), an A/D converter, and I/O ports as on-chip peripheral modules required for
system configuration.
A flash memory (F-ZTAT
the flash memory are connected to a 16-bit bus, enabling byte data and word data to be accessed in
a single state. This improves the instruction fetch and process speeds.
TM
Note: * F-ZTAT
Target Users: This manual was written for users who use this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical
circuits, logic circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on Reading this Manual:
• In order to understand the overall functions of the chip
Read this manual in the order of the table of contents. This manual can be roughly categorized
into the descriptions on the CPU, system control functions, peripheral functions, and electrical
characteristics.
Rev.1.00, 09/03, page vi of xxxviii
TM
*) version is available for this LSI's 256-kbyte ROM. The CPU and
is a trademark of Renesas Technology Corp.
Preface
2
C bus
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