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• Timer control register (TCR)
• Timer output compare control register (TOCR)
Note: OCRA_0 (OCRA_1) and OCRB_0 (OCRB_1) share the same address. Register selection
is controlled by the OCRS bit in TOCR_0 (TOCR_1). ICRA_0 (ICRA_1), ICRB_0
(ICRB_1), and ICRC_0 (ICRC_1) share the same addresses with OCRAR_0 (OCRAR_1),
OCRAF_0 (OCRAF_1), and OCRDM_0 (OCRDM_1). Register selection is controlled by
the ICRS bit in TOCR_0 (TOCR_1).
10.3.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the OVF flag in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot
be accessed in 8-bit units. FRC is initialized to H'0000.
10.3.2
Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the OCFA or OCFB flag in TCSR is set to 1. If the OEA or
OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by
the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB).
Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR
should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to
H'FFFF.
10.3.3
Input Capture Registers A to D (ICRA to ICRD)
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only
register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID)
is detected, the current FRC value is transferred to ICRA to ICRD. At the same time, the ICFA to
ICFD flags in TCSR are set to 1. The FRC contents are transferred to ICR regardless of the value
of ICF. The input capture edge is selected by the IEDGA to IEDGD bits in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of the
BUFEA and BUFEB bits in TCR.
For example, if an input capture occurs when ICRA is specified as the input capture register and
ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then
transferred to the buffer register ICRC. In this case, setting the IEDGA and IEDGC bits in TCR to
the different values enables the rising- or falling-edge sensing to be specified.
Rev. 1.00, 09/03, page 242 of 704
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