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24.3.3
Bus Timing
Table 24.6 shows the bus timing.
Table 24.6 Bus Timing (Normal Extension)
Condition:
V
= 3.0 V to 3.6 V, V
CC
Item
Address delay time
Address setup time
Address hold time
CS delay time
AS delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 2
Read data access time 3
Read data access time 4
Read data access time 5
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
= 0 V, φ = 5 MHz to 20 MHz
SS
Symbol
Min.
t
AD
t
0.5 x t
–15
AS
cyc
t
0.5 x t
– 10
AH
cyc
t
CSD
t
ASD
t
RSD1
t
RSD2
t
15
RDS
t
0
RDH
t
ACC2
t
ACC3
t
ACC4
t
ACC5
t
WRD1
t
WRD2
t
1.0 x t
–20
WSW1
cyc
t
1.5 x t
–20
WSW2
cyc
t
WDD
t
0
WDS
t
10
WDH
t
30
WTS
t
5
WTH
Max.
Unit
20
ns
20
20
20
20
1.5 x t
– 25
cyc
2.0 x t
– 30
cyc
2.5 x t
– 25
cyc
3.0 x t
– 30
cyc
20
20
30
Rev. 1.00, 09/03, page 677 of 704
Test Conditions
Figures 24.8 to
24.10
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