Renesas H8S/2437 Hardware Manual page 468

Bit Bit Name
3 STOP
2 MP
1 CKS1
0 CKS0
Rev. 1.00, 09/03, page 430 of 704
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked
regardless of the STOP bit setting. If the second
stop bit is 0, it is treated as the start bit of the next
transmit frame.
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
Clock Select 1, 0
These bits select the clock source for the baud
rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the CKS bit settings and
the baud rate, see section 16.3.9, Bit Rate
Register (BRR). n is the decimal display of the
value of n in BRR (see section 16.3.9, Bit Rate
Register (BRR)).