Renesas H8S/2437 Hardware Manual page 190

TPU channel (2)
0 setting
MD3 to MD0
IOC3 to IOC0 B'0000
B'0100
B'1xxx

CCLR2 to
CCLR0

Output
function
[Legend]
x: Don't care
Notes: 1. When TIOCC0/TCLKAS = 0, MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx, this
pin functions as the TIOCC0 input pin.
2. When TIOCC0/TCLKAS = 0 and TPSC2 to TPSC0 in one of TCR_0 to TCR2 = B'100,
this pin functions as the TCLKA input pin. When TIOCC0/TCLKAS = 0 and phase-count
mode is set to the TCR channel 1, this pin functions as the TCLKA input pin.
3. Output is disabled for TIOCD0. When BFA = 1 or BFB = 1 in TMDR0, output is disabled
and the setting is the same as (2).
• P21/TIOCB0/A9/AD9
When the TIOCB0S bit in PTCNT2 is cleared to 0, this pin can be used as the TIOCB0 pin.
According to operating modes, the TPU channel 0 settings by the MD3 to MD0 bits in
TMDR_0 and the IOB3 to IOB0 bits in TIORH_0, and the combination of the TIOCB0S bit
and the P21DDR bit, pin functions change as follows.
• Extended Mode (EXPE = 1)
Normal Extended Mode (ADMXE = 0)
P21DDR
Pin function P21 input pin
• Single-Chip Mode (EXPE = 0)
TIOCB0S
TPU channel
0 setting
P21DDR
Pin function P21 input pin
Rev. 1.00, 09/03, page 152 of 704
(1)
B'0000
B'0001 to B'0011
B'0101 to B'0111

Output compare
output
0
A9 output pin
0
Table below (2)
0 1
P21 output pin
TIOCB0 input pin*
(2) (1)
B'001x B'0010
B'xx00 Other
than
B'xx00
 

PWM*
mode 1
output
Multiplex Extended Mode (ADMXE = 1)
1
TIOCB0 input pin*
Table below (1)

TIOCB0 output
pin
(1)
B'0011
Other than B'xx00
Other than B'101
B'101
3
PWM
mode 2
output

AD9 I/O pin
1
0
P21 input pin P21 output pin
(2)


1