T
AD15 to AD8
AD7 to AD0
Note:
n = 1 to 3
Figure 6.24 Bus Timing for 16-Bit, 3-State Data Access Space (3)
Rev. 1.00, 09/03, page 124 of 704
Read Cycle
Data
Address
T
T
T
T
1
AW
2
3
Address
Address
(Word Access, with Address Wait)
Address
T
T
T
T
4
DSW
5
1
Data
Address
Data
Address
Write Cycle
Data
T
T
T
T
AW
2
3
4
Data
Data
T
DSW
5