Influences On Absolute Accuracy; Setting Range Of Analog Power Supply And Other Pins; Notes On Board Design; Notes On Noise Countermeasures - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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18.7.3

Influences on Absolute Accuracy

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not interfere with digital signals on the
mounting board, so acting as antennas.
18.7.4

Setting Range of Analog Power Supply and Other Pins

If conditions shown below are not met, the reliability of the LSI may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ ANn ≤ Vref.
• Relation between AVcc, AVss and Vcc, Vss
For the relationship between AVcc, AVss and Vcc, Vss, set AVcc ≥ Vcc and AVss = Vss. If
the A/D converter is not used, the AVcc and AVss pins must not be open.
• Vref setting range
The reference voltage at the Vref pin should be set in the range Vref ≤ AVcc.
18.7.5

Notes on Board Design

In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must be isolated from the analog input pins (AN0 to AN15), analog
reference power supply (Vref), and analog power supply voltage (AVcc) by the analog ground
(AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital
ground (Vss) on the board.
18.7.6

Notes on Noise Countermeasures

A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN15) should be connected between AVcc and AVss as
shown in figure 18.7. Also, the bypass capacitors connected to AVcc and the filter capacitor
connected to AN0 to AN15 must be connected to AVss.
Rev. 1.00, 09/03, page 521 of 704

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