Port Control Descriptions; Port Configuration Register (Gpacon-Gpmcon); Port Data Register (Gpadat-Gpmdat); Port Pull-Up/Down Register (Gpbudp-Gpmudp) - Samsung S3C2416 User Manual

I/O PORTS

2 PORT CONTROL DESCRIPTIONS

2.1 PORT CONFIGURATION REGISTER (GPACON-GPMCON)

In S3C2416X, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins.
The GPxCON(port control register) determines which function is used for each pin.
If GPF0 – GPF7, GPG0 – GPG7 is used for the wakeup signal in Sleep/Stop/DeepStop mode, these ports must
be configured in EINT.

2.2 PORT DATA REGISTER (GPADAT-GPMDAT)

If ports are configured as output ports, data can be written to the corresponding bit of GPxDAT. If Ports are
configured as input ports, the data can be read from the corresponding bit of GPxDAT.

2.3 PORT PULL-UP/DOWN REGISTER (GPBUDP-GPMUDP)

The port pull-up/down register controls the pull-up/down resister enable/disable of each port group. When the
corresponding bit is 0, the pull-down resister of the pin is enabled. When 1, the pull-down resister is disabled.
If the port pull-down register is enabled then the pull-down resisters work without pin's functional setting(input,
output, DATAn, EINTn and etc)

2.4 MISCELLANEOUS CONTROL REGISTER

This register controls mode selection, and CLKOUT selection.

2.5 EXTERNAL INTERRUPT CONTROL REGISTER

The 16 external interrupts are requested by various signaling methods. The EXTINT register configures the
signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both
edge trigger for the external interrupt request
Because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal that
is longer than 3 clocks.
EINT[15:0] are used for wakeup sources from Sleep/Stop/DeepStop mode.
Caution
I/O ports In VDD_SD power domain release retention automatically when I/O ports are waken up from sleep
mode. In Stop/DeepStop/Sleep mode GPA/GPK status are controlled by PDSMCON/PDDMCON. They control
GPA/GPK as a few groups. For example like GPA1 and GPA2 individual control is impossible in sleep
10-8
S3C2416 RISC MICROPROCESSOR
mode.