Subclock Input Circuit; Waveform Forming Circuit; Figure 19.7 Subclock Input Timing; Table 19.5 Subclock Input Conditions - Renesas H8S/2111B Hardware Manual

19.5

Subclock Input Circuit

The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
Subclock input conditions are shown in table 19.5. When the subclock is not used, subclock input
should not be enabled.

Table 19.5 Subclock Input Conditions

Item
Subclock input pulse width
low level
Subclock input pulse width
high level
Subclock input rising time
Subclock input falling time
EXCL
19.6

Waveform Forming Circuit

To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
Rev. 1.00, 05/04, page 460 of 544
Symbol Min
t —
EXCLL
t —
EXCLH
t —
EXCLr
t —
EXCLf
t
EXCLH
t
EXCLr

Figure 19.7 Subclock Input Timing

Vcc = 3.0 to 3.6 V
Typ Max
15.26 —
15.26 —
— 10
— 10
t
EXCLL
t
EXCLf
Measurement
Unit Condition
µs
Figure 19.7
µs
ns
ns
V × 0.5
CC