Chip Select Expansion Control Register (Cse) - Renesas M16C/64C User Manual

M16C/64C Group
11.2.2

Chip Select Expansion Control Register (CSE)

Chip Select Expansion Control Register
b7 b6 b5 b4 b3 b2 b1
Set the CSiW bit (i = 0 to 3) in the CSR register to 0 (wait state) before writing to bits CSEi1W to
CSEi0W. To set the CSiW bit to 1 (no wait state), set bits CSEi1W to CSEi0W to 00b first, and then set
the CSiW bit to 1.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0
Symbol
CSE
Bit Symbol Bit Name
CSE00W
CS0 wait expansion bit
CSE01W
CSE10W
CS1 wait expansion bit
CSE11W
CSE20W
CS2 wait expansion bit
CSE21W
CSE30W
CS3 wait expansion bit
CSE31W
Address
001Bh
b1 b0
0 : 1 wait (1 φ + 1 φ )
0
1 : 2 waits (1 φ + 2 φ )
0
0 : 3 waits (1 φ + 3 φ )
1
1 1 : Do not set.
b3 b2
0 : 1 wait (1 φ + 1 φ )
0
1 : 2 waits (1 φ + 2 φ )
0
0 : 3 waits (1 φ + 3 φ )
1
1 1 : Do not set.
b5 b4
0 : 1 wait (1 φ + 1 φ )
0
1 : 2 waits (1 φ + 2 φ )
0
0 : 3 waits (1 φ + 3 φ )
1
1 1 : Do not set.
b7 b6
0 : 1 wait (1 φ + 1 φ )
0
1 : 2 waits (1 φ + 2 φ )
0
0 : 3 waits (1 φ + 3 φ )
1
1 1 : Do not set.
Reset Value
00h
Function
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