External Bus Status When Internal Area Accessed; Software Wait - Renesas M16C/6NK Hardware Manual

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M16C/6N Group (M16C/6NK, M16C/6NM)

7.2.9 External Bus Status When Internal Area Accessed

Table 7.7 shows the external bus status when the internal area is accessed.
Table 7.7 External Bus Status When Internal Area Accessed
Item
A0 to A19
D0 to D15 When read High-impedance
When write Output data
_____ ______ ________ _________
RD, WR, WRL, WRH
________
BHE
_______ _______
CS0 to CS3
ALE

7.2.10 Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See
Table 7.8 Bit and Bus Cycle Related to Software Wait for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to "0" (with wait state). Figure 7.6 shows
the CSE register. Table 7.8 shows the software wait related bits and bus cycles. Figures 7.7 and 7.8 show
the typical bus timings using software wait.
Chip Select Expansion Control Register
b7 b6 b5 b4 b3
NOTES:
1. Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W
bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "00b" before
setting it.
2. Not available this register in T/V-ver..
Figure 7.6 CSE Register
Rev.2.00 Nov 28, 2005
REJ09B0124-0200
SFR Accessed
Address output
_____ ______ _________ __________
RD, WR, WRL, WRH output
________
BHE output
Output "H"
Output "L"
b2 b1 b0
Symbol
CSE
Bit Symbol
CSE00W
CS0 Wait Expansion Bit
CSE01W
CSE10W
CS1 Wait Expansion Bit
CSE11W
CS20WE
CS2 Wait Expansion Bit
CSE21W
CSE30W
CS3 Wait Expansion Bit
CSE31W
page 52 of 378
Internal ROM, Internal RAM Accessed
Maintain status before accessed address
of external area or SFR
High-impedance
Undefined
Output "H"
Maintain status before accessed status of
external area or SFR
Output "H"
Output "L"
(2)
Address After Reset
001Bh 00h
Bit Name
b1 b0
0 0 : 1 wait
0 1 : 2 waits
(1)
1 0 : 3 waits
1 1 : Do not set a value
b3 b2
0 0 : 1 wait
0 1 : 2 waits
(1)
1 0 : 3 waits
1 1 : Do not set a value
b5 b4
0 0 : 1 wait
0 1 : 2 waits
(1)
1 0 : 3 waits
1 1 : Do not set a value
b7 b6
0 0 : 1 wait
0 1 : 2 waits
(1)
1 0 : 3 waits
1 1 : Do not set a value
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
7. Bus