Table 2. Base Register 0 (Br0) Relevant Bits (Mc68360) - Texas Instruments TMS320C6000 Manual

All internal memory and registers of the MC68360 occupy a single 8K-byte memory block that
can be relocated along 8K-byte boundaries. The location is fixed by writing the desired base
address of the 8K-byte memory block to the MBAR. The 8K-byte block is divided into two
4K-byte sections. The RAM occupies the first section; the internal registers occupy the second
section. The LSB (least significant bit) of the MBAR register indicates when the contents of the
MBAR are valid (if the bit is equal to one the content is valid).
The MC68360's general-purpose chip-selects are controlled by the global memory register
(GMR) and the memory controller status register (MSTAT). There is one GMR and MSTAT in the
memory controller. The MSTAT reports write-protect violations and parity errors for all banks.
The 32-bit read-write GMR contains selections that are common to the entire memory controller.
The GMR is used to control global parameters for memory banks. The DPS bit field of the GMR
register must be set to DPS[1:0] = 11 to enable external DSACKx response. The PBEE bit of the
GMR register should be set to zero to disable parity bus error detection.
The 32-bit read-write GMR contains selections that are common to the entire memory controller.
The GMR is used to control global parameters for memory banks.
The MSTAT reports write-protect violations and parity errors for all banks.
The configuration of the BR and OR registers is shown in Table 2 and Table 3.

Table 2. Base Register 0 (BR0) Relevant Bits (MC68360)

Bit Field
CSNTQ CS negate timing
This bit is used to determine when CS is negated
during
QUICC/MC68030-type bus-master write cycle.
TRLXQ Timing relax
This bit delays the beginning of the internal QUICC
or external QUICC/MC68030-type bus-master cycle
to relax the timing constraints on the user.
V Valid bit
PAREN Parity checking enable
BA31-BA11 Base address
The base address field, the upper 21 bits of each BR,
and the function field are compared to the address on
address bus to determine if a DRAM/SRAM region is
being accessed by an internal QUICC master.
The option register is 32-bit read-write register that may be accessed at any time.
Description
an internal QUICC or
Set to 0 (CS negated normally).
external
Set to 0 (do not relax timing).
1 = content of BR0 and OR0 pair is valid
0 = parity checking disabled
TMS320C6000 Host Port to MC68360 Interface
SPRA545A
Value
5