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Texas Instruments SM320C6455-EP Data Manual

Texas Instruments SM320C6455-EP Data Manual

Fixed-point digital signal processor
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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
Data Manual
JANUARY 2008
SPRS462B

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Summary of Contents for Texas Instruments SM320C6455-EP

  • Page 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B...
  • Page 2 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not...

  • Page 3: Table Of Contents

    Bandwidth Management Power-Down Control Megamodule Resets Megamodule Revision C64x+ Megamodule Register Description(s) Device Operating Conditions Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) FIXED-POINT DIGITAL SIGNAL PROCESSOR Contents SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Contents...
  • Page 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) C64x+ Peripheral Information and Electrical Specifications Parameter Information 7.1.1 3.3-V Signal Transition Levels...
  • Page 5 Timers Device-Specific Information 7.15.2 Timers Peripheral Register Description(s) 7.15.3 Timers Electrical Data/Timing 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information 7.16.2 VCP2 Peripheral Register Description(s) FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SM320C6455-EP Contents...
  • Page 6 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information 7.17.2 TCP2 Peripheral Register Description(s) 7.18 Peripheral Component Interconnect (PCI) 7.18.1 PCI Device-Specific Information 7.18.2 PCI Peripheral Register Description(s) 7.18.3...

  • Page 7: Sprs462B – September 2007 – Revised January

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. C64x+, JTAG, C64x+, VelociTI, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date.

  • Page 8: Ztz/Gtz Bga Package (Bottom View)

    C6000™ DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™...
  • Page 9 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply-accumulates (MACs) every clock cycle.

  • Page 10: Functional Block Diagram

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Functional Block Diagram Figure 1-2 shows the functional block diagram of the C6455 device. DDR2 SDRAM DDR2 Mem Ctlr SBSRAM PLL2 and PLL2 ZBT SRAM Controller EMIFA...

  • Page 11: Device Overview

    (1) The extended temperature device's (A-1000) electrical characteristics and ac timings are the same as those for the corresponding commercial temperature devices (-1000). Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C6455...

  • Page 12: Cpu (Dsp Core) Description

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1. Characteristics of the C6455 Processor (continued) HARDWARE FEATURES Process Technology Product Preview (PP), Advance Information (AI), Product Status or Production Data (PD) (For more details on the C64x+™ DSP part...
  • Page 13 TMS320C64x+ Megamodule Reference Guide (literature number SPRU871) TMS320C6455 Technical Reference (literature number SPRU965) TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84) Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Device Overview...
  • Page 14 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Data path A Data path B A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.

  • Page 15: Memory Map Summary

    256K - 512 128K 128K 256K 256K 256K SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HEX ADDRESS RANGE 0000 0000 - 000F FFFF 0010 0000 - 0010 7FFF 0010 8000 - 007F FFFF 0080 0000 - 009F FFFF...
  • Page 16 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2. C6455 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION EMAC Descriptor Memory Reserved RapidIO Control Registers Reserved RapidIO CPPI RAM Reserved Reserved Reserved Reserved Reserved McBSP 0 Data...

  • Page 17: Boot Sequence

    FIXED-POINT DIGITAL SIGNAL PROCESSOR Section 7.6, Reset Controller. (Section 3.4), PLL1 and PLL2 Controller registers 7.8) cannot be accessed through any host interface, including HPI and PCI. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4.1, Boot Modes Device Overview...
  • Page 18 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 software such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host.

  • Page 19: 2Nd-Level Bootloaders

    TI offers a few second-level bootloaders, such as an EMAC bootloader and a UTOPIA bootloader, which can be loaded using the Master I2C boot. Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...

  • Page 20: Pin Assignments

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Pin Assignments 2.5.1 Pin Map Figure 2-2 through Figure 2-5 GP[5] FSX0 CLKS DD33 GP[4] FSR0 FSX1/ CLKR0 GP[7] GP[6] GP[11] CLKR1/ HD11/ DD33 AD11 GP[0] HD22/...
  • Page 21 RIORX0 RIOTX2 RIOTX1 RIOTX1 DD33 RIOTX0 RIOTX0 RSV17 DD33 DD33 DD33 DD33 DD33 DD33 DD33 DD33 SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 AED5 AED6 AED20 DD33 AED14 AED2 AED18 DD33 AED3 AED9 AED16 AED1 AED10 AED15 DD33...
  • Page 22 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DD18 DD18 RSV19 DD18 DEODT0 DEA4 DLL2 DEA8 DEA5 DEA0 DED19 DEA9 DEA6 DEA1 DED18 DEA10 DEA7 DEA2 DED16 DEA11 DEODT1 DEA3 DED17 Figure 2-4. C6455 Pin Map (Bottom View) [Quadrant C]...
  • Page 23 DED9 DD15 RSV25 DED15 DSDDQM1 DED8 DSDDQ RSV24 DED12 DD15 DD18 GATE1 DSDDQ RSV21 DED13 GATE0 SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 RSV05 RSV04 DD18 DD18 DD18 DD18 DD18 DSDDQS0 RSV18 DCE0 DD18 DD18 DED7 DSDDQS0 DED3...

  • Page 24: Signal Groups Description

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Signal Groups Description CLKIN1 SYSCLK4/GP[1] PLLV1 CLKIN2 PLLV2 TRST EMU0 EMU1 EMU14 EMU15 EMU16 EMU17 EMU18 A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
  • Page 25 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Timer 1 Timer 0 Timers (64-Bit) GPIO General-Purpose Input/Output 0 (GPIO) Port Transmit Clock Receive RAPID IO SM320C6455-EP TOUTL0 TINPL0 GP[7] GP[6] GP[5] GP[4] CLKX1/GP[3] URADDR4/PCBE0/GP[2] SYSCLK4/GP[1] CLKR1/GP[0]...
  • Page 26 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 AED[63:0] ACE5 ACE4 ACE3 ACE2 AEA[19:0] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 ABA[1:0] DED[31:0] DCE0 DEA[13:0] DSDDQM3 DSDDQM2 DSDDQM1 DSDDQM0 A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6455 device.
  • Page 27 SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (Host-Port Interface) Data Register Select Control Half-Word Select McBSP1 McBSP0 Transmit Transmit Receive Receive Clock Clock McBSPs (Multichannel Buffered Serial Ports) SM320C6455-EP HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME CLKX0 FSX0 CLKR0 FSR0 Device Overview...
  • Page 28 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 UXDATA[7:2]/MTXD[7:2], UXDATA[1:0]/MTXD[1:0]/RMTXD[1:0] URDATA[7:2]/MRXD[7:2], URDATA[1:0]/MRXD[1:0]/RMRXD[1:0] URSOC/MRXER/RMRXER, URCLAV/MCRS/RMCRSDV, UXENB/MTXEN/RMTXEN RGTXCTL, RGRXCTL UXCLK/MTCLK/RMREFCLK, A. RGMII signals are mutually exclusive to all other EMAC signals. B. These EMAC pins are muxed with the UTOPIA peripheral. By default, these signals function as EMAC. For more details on these muxed pins, see the Device Configuration section of this document.
  • Page 29 Clock Figure 2-11. UTOPIA Peripheral Signals Data/Address Clock Command Byte Enable Control Arbitration Error PCI Interface Figure 2-12. PCI Peripheral Signals SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 UXDATA7/MTXD7 UXDATA6/MTXD6 UXDATA5/MTXD5 UXDATA4/MTXD4 UXDATA3/MTXD3 UXDATA2/MTXD2 UXDATA1/MTXD1/RMTXD1 UXDATA0/MTXD0/RMTXD0 UXENB/MTXEN/RMTXEN UXADDR4/GMDCLK...

  • Page 30: Terminal Functions

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Terminal Functions The terminal functions table numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information...
  • Page 31 Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z) UTOPIA received address pin 3 (URADDR3) (I) or PCI bus request (O/Z) or GP[15] (I/O/Z) [default] SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 32 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME URADDR2/PINTA I/O/Z GP[14] URADDR1/PRST/ I/O/Z GP[13] URADDR0/PGNT/ I/O/Z GP[12] URADDR4/PCBE0/ I/O/Z GP[2] UXADDR2/PCBE3 I/O/Z UXADDR1/PIDSEL UXADDR0/PTRDY I/O/Z HD31/AD31 HD30/AD30 HD29/AD29 HD28/AD28 HD27/AD27 HD26/AD26 HD25/AD25...
  • Page 33 – If R_ENABLE = 0, then the ASADS/ASRE signal functions as the ASADS signal. – If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 34 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME AEA19/BOOTMODE3 AEA18/BOOTMODE2 AEA17/BOOTMODE1 AEA16/BOOTMODE0 AEA15/AECLKIN_SEL AEA14/HPI_WIDTH AEA13/LENDIAN AEA12/UTOPIA_EN AEA11 Device Overview Table 2-3. Terminal Functions (continued) IPD/IPU EMIFA (64 BIT) - ADDRESS EMIFA external address (word address) (O/Z)
  • Page 35 If the SRIO peripheral is not used and the SRIO supply pins are connected to V , the AEA3 pin must be pulled down to V resistor. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION 3, Device Configuration.
  • Page 36 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME AED63 AED62 AED61 AED60 AED59 AED58 AED57 AED56 AED55 AED54 AED53 AED52 AED51 AED50 AED49 AED48 AED47 AED46 AED45 AED44 AED43 I/O/Z AED42 AED41...
  • Page 37 Byte-write enables for most types of memory. Can be directly connected to SDRAM read and write mask signal (SDQM). SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 38 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME DSDDQS3 I/O/Z DSDDQS2 I/O/Z DSDDQS1 I/O/Z DSDDQS0 I/O/Z DSDDQS3 I/O/Z DSDDQS2 I/O/Z DSDDQS1 I/O/Z DSDDQS0 I/O/Z DEA13 DEA12 DEA11 DEA10 DEA9 DEA8 DEA7 DEA6...
  • Page 39 INTER-INTEGRATED CIRCUIT (I2C) I2C clock. When the I2C module is used, use an external pullup resistor. I2C data. When I2C is used, ensure there is an external pullup resistor. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 40 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0) CLKS MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKR1/GP[0] I/O/Z FSR1/GP[10]...
  • Page 41 EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9] pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details, Section 3, Device Configuration). SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 42 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME RIOCLK AF15 RIOCLK AG15 RIOTX3 AF17 RIOTX2 AG18 RIOTX1 AG22 RIOTX0 AF23 RIOTX3 AF18 RIOTX2 AG19 RIOTX1 AG21 RIOTX0 AF22 RIORX3 AH18 RIORX2 AJ18...
  • Page 43 When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these pins function as EMAC transmit data pins (MTXD[x:0]) (O) for MII, RMII, or GMII. MACSEL[1:0] dependent. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 44 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configuration pins — the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC/MDIO interface.
  • Page 45 Reserved. This pin must be connected to the 1.8-V I/O supply (DV resistor for proper device operation. Reserved. This pin must be connected directly to ground for proper device operation. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION ) via a 200-...
  • Page 46 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME DDMON DD33MON DD15MON DD18MON REFSSTL REFHSTL AD20 AC15 AC17 AD16 DLL1 DLL2 Device Overview Table 2-3. Terminal Functions (continued) IPD/IPU SUPPLY VOLTAGE MONITOR PINS Die-side 1.2-V core supply (CV...
  • Page 47 However, connecting these pins directly to ground prevents boundary-scan from functioning on the RGMII pins of the EMAC. To preserve boundary-scan functionality on the RGMII pins, see 1.8-V I/O supply voltage (DDR2 Memory Controller) SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION DD15...
  • Page 48 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME DD33 AA23 AB24 AC11 AC13 AC19 AC21 AC23 AC29 Device Overview Table 2-3. Terminal Functions (continued) IPD/IPU 3.3-V I/O supply voltage www.ti.com DESCRIPTION Submit Documentation Feedback...
  • Page 49 FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 2-3. Terminal Functions (continued) IPD/IPU 3.3-V I/O supply voltage 1.25-V core supply voltage (-1000 and -1200 devices) 1.2-V core supply voltage (-850 and -720 devices) SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 50 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME Device Overview Table 2-3. Terminal Functions (continued) IPD/IPU 1.25-V core supply voltage (-1000 and -1200 devices) 1.2-V core supply voltage (-850 and -720 devices)
  • Page 51 SIGNAL TYPE NAME Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 2-3. Terminal Functions (continued) IPD/IPU Ground pins SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 52 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME Device Overview Table 2-3. Terminal Functions (continued) IPD/IPU Ground pins www.ti.com DESCRIPTION Submit Documentation Feedback...
  • Page 53 SIGNAL TYPE NAME AA24 AB23 AC10 AC12 AC14 AC16 AC18 Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 2-3. Terminal Functions (continued) IPD/IPU Ground pins SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION Device Overview...
  • Page 54 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SIGNAL TYPE NAME AC20 AC22 AC24 AC28 AD13 AD15 AD17 AD19 AD21 AD23 AE16 AE18 AE20 AE22 AE24 AF19 AF21 AG13 AG16 AG20 AG24 AH15 AH19 AH21...

  • Page 55: Development

    Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

  • Page 56: Documentation Support

    C64x+™ DSP generation member. For device part numbers and further ordering information for SM320C6455-EP in the ZTZ/GTZ package type, see the TI website (www.ti.com) or contact your TI sales representative.
  • Page 57 (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP) in some of the digital Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 58 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 signal processor (DSPs) of the C6000™ DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP.

  • Page 59: Device Configuration

    AECLKIN (default mode) SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK4 is selected as CPU/8 clock rate. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4, Boot Sequence.
  • Page 60 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ AEA14 AEA13 AEA12 AEA11 [M25, AEA[10:9] M27] AEA8 AEA7 AEA6 AEA5 Device Configuration FUNCTIONAL DESCRIPTION HPI peripheral bus width select (HPI_WIDTH).

  • Page 61: Peripheral Configuration At Device Reset

    EMIFA peripheral pins are disabled (default) EMIFA peripheral pins are enabled Section 7.7, PLL1 and PLL1 Controller, and SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 , the AEA3 pin must be pulled down to V Section 7.8,PLL2 and PLL2...
  • Page 62 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) CONFIGURATION PIN SETTING PCI66 PCI_EEAI PCI_EN PIN AEA6 PIN AEA8 PIN [Y29] [U27] [P25] (1) PCI_EEAI is latched at reset as a configuration input. If PCI_EEAI is set as one, then default values are loaded from an external I2C EEPROM.

  • Page 63: Peripheral Selection After Device Reset

    Clock to the peripheral is turned on and the peripheral is taken out of reset. Not a user-programmable state. This is an intermediate state when transitioning from an disabled state to an enabled state. SM320C6455-EP Table 3-4. PERIPHERALS THAT CAN BE IN THIS STATE...
  • Page 64 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Reset Figure 3-1. Peripheral Transitions Between States Figure 3-2 shows the flow needed to change the state of a given peripheral on the C6455 device. A 32 bit key (value = 0x0F0A 0B00) must be written to the Peripheral Lock register (PERLOCK) in order to allow access to the PERCFG0 register.

  • Page 65: Device State Control Registers

    Table 3-5. Device State Control Registers ACRONYM PERLOCK PERCFG0 PERSTAT0 PERSTAT1 EMACCFG PERCFG1 EMUBUFPD SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME Reserved Peripheral Lock Register Peripheral Configuration Register 0 Reserved Reserved Peripheral Status Register 0 Peripheral Status Register 1...

  • Page 66: Peripheral Lock Register Description

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.1 Peripheral Lock Register Description When written with correct 32 bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles.

  • Page 67: Peripheral Configuration Register 0 Description

    FIXED-POINT DIGITAL SIGNAL PROCESSOR NOTE Reserved PCICTL Reserved R/W-0 R/W-0 I2CCTL Reserved R/W-0 R/W-0 EMACCTL Reserved R/W-0 R/W-0 SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 R/W-0 HPICTL Reserved McBSP1CTL R/W-0 R/W-0 GPIOCTL Reserved TIMER1CTL R/W-0 R/W-0 VCPCTL Reserved...
  • Page 68 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Field Value Description McBSP1CTL Mode control for McBSP1 Set McBSP1 to disabled mode Set McBSP1 to enabled mode Reserved Reserved.

  • Page 69: Peripheral Configuration Register 1 Description

    EMIFA 8 bit ROM boot is used (BOOTMODE[3:0] = 0100b). Set EMIFA to disabled Set EMIFA to enabled Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Reserved R-0x00 Reserved R-0x00 SM320C6455-EP DDR2CTL EMIFACTL R/W-0 R/W-0 Device Configuration...

  • Page 70: Peripheral Status Registers Description

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.4 Peripheral Status Registers Description The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals. Reserved McBSP0STAT GPIOSTAT TIMER1STAT EMACSTAT LEGEND: R = Read only; -n = value after reset Figure 3-6.
  • Page 71 TCP is in the enabled state TCP is in the static powerdown state TCP is in the enable in progress state Others Reserved Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Device Configuration...
  • Page 72 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Reserved LEGEND: R = Read only; -n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions...

  • Page 73: Emac Configuration Register (Emaccfg) Description

    RMII logic reset is asserted. 17:0 Reserved Reserved. Writes to this register must keep this bit as 0. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Reserved R/W-0 RMII_RST R/W-1 Reserved R/W-0 SM320C6455-EP Reserved R/W-0 Device Configuration...

  • Page 74: Emulator Buffer Powerdown Register (Emubufpd) Description

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2]. These buffers can be powered down if the device trace feature is not needed.

  • Page 75: Device Status Register Description

    Reserved. Read-only, writes have no effect. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 3-13. Reserved R-0000 0000 PCI_EN CFGGP2 Reserved PCI_EEAI AECLKINSEL BOOTMODE3 SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 CFGGP1 CFGGP0 Reserved MAC_SEL1 MAC_SEL0 Reserved BOOTMODE2 BOOTMODE1 BOOTMODE0 Section Device Configuration...
  • Page 76 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Field Value Description SYSCLKOUT_EN SYSCLKOUT Enable (SYSCLKOUT_EN) status bit Shows the status of which function is enabled on the SYSCLK4/GP[1] muxed pin.

  • Page 77: Jtag Id (Jtagid) Register Description

    Part Number (16 Bit) value. C6455 value: 0000 0000 1000 1010b. Manufacturer (11 Bit) value. C6455 value: 0000 0010 111b. LSB. This bit is read as a "1" for C6455. SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4, Boot...

  • Page 78: Pullup/Pulldown Resistors

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Pullup/Pulldown Resistors Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The C6455 device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
  • Page 79 AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK4 pin function) AEA[3] = 1 (must oppose IPD) AEA[2:0] (CFGGP[2:0]) = 000 (default) TIMERS + RapidIO + EMAC (MII) + MDIO) SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 AED[63:0] AECLKIN, AARDY , AHOLD...
  • Page 80 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HD[31:0] HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 GP[15:12,2,1] CLKIN1, PLLV1 SYSCLK4 CLKR1, FSR1, DR1, CLKS1, DX1, FSX1, CLKX1 CLKR0, FSR0, DR0, CLKS0, DX0, FSX0, CLKX0...

  • Page 81: System Interconnect

    VCP2, a bridge is required to connect the data SCR to the 64-bit configuration bus interface. Note that some peripherals can be accessed through the data SCR and also through the configuration SCR. Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 4.2).

  • Page 82: Data Switch Fabric Connections

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Data Switch Fabric Connections Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency.
  • Page 83 Data SCR (SYSCLK2) (SYSCLK2) (SYSCLK2) 128-bit (SYSCLK2) (SYSCLK3) (SYSCLK3) Bridge Bridge 128 (SYSCLK2) (SYSCLK2) (SYSCLK3) (SYSCLK2) SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SLAVE 64 (SYSCLK2) Bridge TCP2 64 (SYSCLK2) Bridge VCP2 32 (SYSCLK2) Bridge 32 (SYSCLK3) McBSPs (SYSCLK3)

  • Page 84: Configuration Switch Fabric

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TCP2 VCP2 McBSPs EMAC SRIO Megamodule (1) Applies to both descriptor and data accesses by the SRIO peripheral. Configuration Switch Fabric Figure 4-2 shows the connection between the C64x+ Megamodule and the configuration switched central resource (SCR).
  • Page 85 FIXED-POINT DIGITAL SIGNAL PROCESSOR CFG SCR (SYSCLK2) 32-bit (SYSCLK3) (SYSCLK2) Bridge 32 (SYSCLK2) (SYSCLK2) 32 (SYSCLK2) 32 (SYSCLK2) (SYSCLK2) SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 32 (SYSCLK2) TCP2 32 (SYSCLK2) VCP2 (SYSCLK3) GPIO (SYSCLK3) McBSPs (SYSCLK3) UTOPIA...

  • Page 86: Bus Priorities

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Bus Priorities On the C6455 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6455 bus masters are shown in the best system performance for a particular application.

  • Page 87: C64X+ Megamodule

    Configuration Registers Slave DMA L1 data memory controller Cache control Bandwidth management Master DMA Memory protection L1D cache/SRAM SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Advanced event triggering (AET) C64x+ CPU Instruction fetch SPLOOP buffer 16/32−bit instruction dispatch...
  • Page 88 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Region 1 size is 32K bytes with no wait states. L1D is a two-way set-associative cache while L1P is a direct-mapped cache. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule.
  • Page 89 1840K bytes SRAM 15/16 SRAM 31/32 SRAM 4-way cache 4-way cache 4-way cache SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Block base L2 memory address 0080 0000h 009C 0000h 128K bytes 009E 0000h 64K bytes 009F 0000h 32K bytes...

  • Page 90: Memory Protection

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Memory Protection Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (64KB each).

  • Page 91: Power-Down Control

    Section 7.6, Reset Controller. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR NOTE Table 5-2. Megamodule Reset (Global or Local) GLOBAL RESET TYPE MEGAMODULE RESET SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 LOCAL MEGAMODULE RESET C64x+ Megamodule...

  • Page 92: Megamodule Revision

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Megamodule Revision The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in...

  • Page 93: C64X+ Megamodule Register Description(S)

    Interrupt Multiplexor Register 3 Reserved AEGMUX0 Advanced Event Generator Mux Register 0 AEGMUX1 Advanced Event Generator Mux Register 1 Reserved INTXSTAT Interrupt Exception Status Register INTXCLR Interrupt Exception Clear Register SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME C64x+ Megamodule...
  • Page 94 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE 0180 0188 0180 0188 - 0180 01BC 0180 01C0 0180 01C4 - 0180 FFFF Table 5-5. Megamodule Powerdown Control Registers...
  • Page 95 Controls EMIFA CE2 Range A300 0000 - A3FF FFFF MAR164 Controls EMIFA CE2 Range A400 0000 - A4FF FFFF MAR165 Controls EMIFA CE2 Range A500 0000 - A5FF FFFF SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME C64x+ Megamodule...
  • Page 96 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE 0184 8298 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 0184 82B8...
  • Page 97 L2 memory protection page attribute register 0 L2MPPA1 L2 memory protection page attribute register 1 L2MPPA2 L2 memory protection page attribute register 2 L2MPPA3 L2 memory protection page attribute register 3 SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME REGISTER NAME C64x+ Megamodule...
  • Page 98 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE 0184 A210 0184 A214 0184 A218 0184 A21C 0184 A220 0184 A224 0184 A228 0184 A22C...
  • Page 99 L1D memory protection page attribute register 28 L1DMPPA29 L1D memory protection page attribute register 29 L1DMPPA30 L1D memory protection page attribute register 30 L1DMPPA31 L1D memory protection page attribute register 31 Reserved SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME C64x+ Megamodule...
  • Page 100 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-10. CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE 0182 0200 0182 0204 0182 0208 0182 020C 0182 0210 - 0182 02FF 0184 1000 0184 1004...

  • Page 101: Device Operating Conditions

    -720 0.49DV 1.8-V operation 1.5-V operation 1.8-V operation 1.5-V operation SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 -0.5 V to 1.5 V -0.5 V to 4.2 V -0.5 V to 2.5 V -0.5 V to 2.5 V -0.5 V to 1.5 V -0.5 V to 2.5 V...
  • Page 102 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions (continued) Supply ground High-level input voltage Low-level input voltage Maximum voltage during overshoot/undershoot (PCI-capable pins) Operating case temperature (1) These rated numbers are from the PCI Local Bus Specification (version 2.3). The DC specifications and AC specifications are defined in Table 4-3 and Table 4-4, respectively, of the PCI Local Bus Specification.

  • Page 103: Electrical Characteristics Over Recommended Ranges Of Supply Voltage And Operating Case Temperature (Unless Otherwise Noted)

    DV , pins with DD33 internal pulldown resistor 0.1DV 0.9DV DD33 DD33 indicates the input leakage current. For bi-directional pins, I SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 0.8DV DD33 0.9DV DD33 - 0.4 DD15 0.22DV DD33 0.1DV...
  • Page 104 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) (continued) PARAMETER AECLKOUT, CLKR1/GP[0], CLKX1/GP[3], SYSCLK4/GP[1], EMU[18:0], CLKR0, CLKX0 EMIF pins (except...

  • Page 105: C64X+ Peripheral Information And Electrical Specifications

    SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Tester Pin Electronics Transmission Line Z0 = 50 (see Note) MAX and V C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Data Sheet Timing Reference Point Output Under Test Device Pin (see Note) = 1.5 V...

  • Page 106: Timing Parameters And Board Routing Analysis

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.1.3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must be taken into account. Timing values may be adjusted by increasing/decreasing such delays.

  • Page 107: Recommended Clock And Control Signal Transition Behavior

    DD33 DD12 supply stable before all other supplies stable DD12 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (or between V and V ) in a monotonic 7-5. After the DV...

  • Page 108: Preserving Boundary-Scan Functionality On Rgmii And Ddr2 Memory Pins

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not possible to disable these peripherals after the boot process is complete.

  • Page 109: Enhanced Direct Memory Access (Edma3) Controller

    McBSPs. Table 4-1 transfer controllers. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 NOTE lists the device resources that can be accessed by each of the C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...

  • Page 110: Edma3 Device-Specific Information

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.4.1 EDMA3 Device-Specific Information The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used.

  • Page 111: Edma3 Peripheral Register Description(S)

    DMA Channel 4 Mapping Register DCHMAP5 DMA Channel 5 Mapping Register DCHMAP6 DMA Channel 6 Mapping Register DCHMAP7 DMA Channel 7 Mapping Register C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 EVENT DESCRIPTION REGISTER NAME...
  • Page 112 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 0120 02A0 0124 02A0 0128 02A0 012C 02A0 0130 02A0 0134 02A0 0138 02A0 013C 02A0 0140...
  • Page 113 DMA Region Access Enable Register High for Region 3 DRAE4 DMA Region Access Enable Register for Region 4 DRAEH4 DMA Region Access Enable Register High for Region 4 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 114 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 0368 02A0 036C 02A0 0370 02A0 0374 02A0 0378 02A0 037C 02A0 0380 02A0 0384 02A0 0388...
  • Page 115 Memory Protection Page Attribute Register 0 MPPA1 Memory Protection Page Attribute Register 1 MPPA2 Memory Protection Page Attribute Register 2 MPPA3 Memory Protection Page Attribute Register 3 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 116 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 081C 02A0 0820 02A0 0824 02A0 0828 02A0 082C - 02A0 0FFC 02A0 1000 02A0 1004...
  • Page 117 Shadow Region 4 Channel Registers Reserved Shadow Region 5 Channel Registers Reserved Shadow Region 6 Channel Registers Reserved Shadow Region 7 Channel Registers Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 118 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HEX ADDRESS RANGE 02A0 4000 - 02A0 401F 02A0 4020 - 02A0 403F 02A0 4040 - 02A0 405F 02A0 4060 - 02A0 407F 02A0 4080 - 02A0 409F...
  • Page 119 Error Register ERREN Error Enable Register ERRCLR Error Clear Register ERRDET Error Details Register ERRCMD Error Interrupt Command Register Reserved RDRATE Read Rate Register Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 120 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE 02A2 8240 02A2 8244 02A2 8248 02A2 824C 02A2 8250 02A2 8254 02A2 8258 02A2 825C...
  • Page 121 Destination FIFO Destination Address Register 2 DFBIDX2 Destination FIFO BIDX Register 2 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 Reserved DFOPT3 Destination FIFO Options Register 3 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 122 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE 02A3 03C4 02A3 03C8 02A3 03CC 02A3 03D0 02A3 03D4 02A3 03D8 - 02A3 7FFF Table 7-9. EDMA3 Transfer Controller 3 Registers...
  • Page 123 Destination FIFO Count Register 3 DFDST3 Destination FIFO Destination Address Register 3 DFBIDX3 Destination FIFO BIDX Register 3 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...

  • Page 124: Interrupts

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic.
  • Page 125 Reserved. These system events are not connected and, therefore, Reserved not used. EFIINTA EFI interrupt from side A EFIINTB EFI interrupt from side B C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION...
  • Page 126 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER INTERRUPT EVENT 102 - 112 114 - 115 IDMA_BUSERR C64x+ Peripheral Information and Electrical Specifications Reserved. These system events are not connected and, therefore, Reserved not used.

  • Page 127: External Interrupts Electrical Data/Timing

    (1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-6. NMI Interrupt Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP (see Figure 7-6) -720 -850...

  • Page 128: Reset Controller

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Reset Controller The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device. The C6455 device has several types of resets: power-on reset, warm reset, max reset, system reset, and CPU reset.

  • Page 129: Warm Reset (Reset Pin)

    4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 NOTE C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...

  • Page 130: Max Reset

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4, Boot Sequence). The POR pin should be held inactive (high) throughout the Warm Reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met.

  • Page 131: Reset Priority

    The rest request priorities are as follows (high to low): Power-on Reset Maximum Reset Warm Reset System Reset CPU Reset Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...

  • Page 132: Reset Controller Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.6.7 Reset Controller Register The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see Table 7-18).

  • Page 133: Reset Electrical Data/Timing

    (1) (2) (3) (see Section 3.7, Pullup/Pulldown Resistors. (see Figure 7-9) PARAMETER Section 7.3.1, Power-Supply Sequencing. C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-8 Figure 7-9) -720 -850 A-1000/-1000 -1200 256D Section 7.6, Reset Controller).
  • Page 134 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Power Supplies Ramping CLKIN1 PCLK RESET RESETSTAT SYSREFCLK (PLL1C) SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) Boot and Device Configuration Pins Z Group Undefined Low Group Undefined High Group...
  • Page 135 Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], and PCI_EN. Figure 7-9. Warm Reset and Max Reset Timing Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...

  • Page 136: Pll1 And Pll1 Controller

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 PLL1 and PLL1 Controller The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel buffered serial ports (McBSPs) and the external memory interface (EMIF).

  • Page 137: Pll1 Controller Device-Specific Information

    /1, /2, ..., /8 CLKDIV (CTRL.[18:16]) (EMIF Input Clock) Figure 7-10. PLL1 and PLL1 Controller C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 PLL1 Controller PLLEN (PLLCTL.[0]) SYSREFCLK (C64x+ MegaModule) DIVIDER D2 SYSCLK2...

  • Page 138: Pll1 Controller Operating Modes

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. SYSCLK5 clocks the emulation and trace logic of the DSP.

  • Page 139: Pll1 Controller Memory Map

    Reserved SYSTAT SYSCLK Status Register Reserved Reserved Reserved PLLDIV4 PLL Controller Divider 4 Register PLLDIV5 PLL Controller Divider 5 Register Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2000*C REGISTER NAME UNIT...

  • Page 140: Pll1 Controller Register Descriptions

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3 PLL1 Controller Register Descriptions This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRUE56).

  • Page 141: Pll Multiplier Control Register

    Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Figure 7-12 Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 and described in Table 7-20. The PLLM PLLM R/W-0h...

  • Page 142: Pll Pre-Divider Control Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.3 PLL Pre-Divider Control Register The PLL pre-divider control register (PREDIV) is shown in PREDEN R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-13.

  • Page 143: Pll Controller Divider 4 Register

    6. Divide frequency by 6. 8. Divide frequency by 8. 10 to 16. Divide frequency by 10 to divide frequency by 16. C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 and described in Table 7-22.

  • Page 144: Pll Controller Divider 5 Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.5 PLL Controller Divider 5 Register The PLL controller divider 5 register (PLLDIV5) is shown in D5EN R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-15.

  • Page 145: Pll Controller Command Register

    Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-24. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Rsvd GOSET R/W-0 R/W-0...

  • Page 146: Pll Controller Status Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.7 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-17.

  • Page 147: Pll Controller Clock Align Control Register

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-18 and described in ALN5 ALN4...

  • Page 148: Plldiv Ratio Change Status Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE.

  • Page 149: Sysclk Status Register

    Reserved. The reserved bit location is always read as 1. A value written to this field has no effect. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 7-28. Reserved Reserved SYS5ON SYS4ON C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SYS3ON SYS2ON Reserved...

  • Page 150: Pll1 Controller Input And Output Clock Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing Table 7-29. Timing Requirements for CLKIN1 Devices Cycle time, CLKIN1 c(CLKIN1) Pulse duration, CLKIN1 high w(CLKIN1H) Pulse duration, CLKIN1 low...

  • Page 151: Pll2 And Pll2 Controller

    TMS320C6455 DSP PLLREF PLLOUT PLL2 PLLM PLL2 Controller Figure 7-23. PLL2 Block Diagram C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TMS320C645x SYSCLK3 (From PLL1 Controller) SYSCLK2 (From PLL1 Controller) DDR2 Memory Controller...

  • Page 152: Pll2 Controller Device-Specific Information

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.1 PLL2 Controller Device-Specific Information 7.8.1.1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7-23, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2 memory controller.

  • Page 153: Sprs462B – September 2007 – Revised January

    PLL Controller Status Register ALNCTL PLL Controller Clock Align Control Register DCHANGE PLLDIV Ratio Change Status Register Reserved Reserved SYSTAT SYSCLK Status Register Reserved Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DESCRIPTION...

  • Page 154: Pll Controller Divider 1 Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.1 PLL Controller Divider 1 Register The PLL controller divider 1 register (PLLDIV1) is shown in D1EN R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-24.

  • Page 155: Pll Controller Command Register

    Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-34. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Rsvd GOSET R/W-0 R/W-0...

  • Page 156: Pll Controller Status Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.3 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-26.

  • Page 157: Plldiv Ratio Change Status Register

    SYSCLK1 ratio has been modified. When GOSET is set, SYSCLK1 will change to the new ratio. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 7-37. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 SYS1...

  • Page 158: Sysclk Status Register

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.6 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-29.

  • Page 159: Pll2 Controller Input Clock Electrical Data/Timing

    Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (1) (2) (3) (see MAX and V Figure 7-30. CLKIN2 Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Figure 7-30) -720 -850 A-1000/-1000 UNIT -1200 37.5...

  • Page 160: Ddr2 Memory Controller

    For the C6455 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met.

  • Page 161: Ddr2 Memory Controller Peripheral Register Description(S)

    DDR2 Memory Controller SDRAM Timing 2 Register Reserved BPRIO DDR2 Memory Controller Burst Priority Register Reserved Reserved Reserved Reserved DMCCTL DDR2 Memory Controller Control Register Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...

  • Page 162: External Memory Interface A (Emifa)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10 External Memory Interface A (EMIFA) The EMIFA can interface to a variety of external devices or ASICs, including: Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM) ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM...

  • Page 163: Emifa Peripheral Register Description(S)

    EMIFA Interrupt RAW Register INTMSK EMIFA Interrupt Masked Register INTMSKSET EMIFA Interrupt Mask Set Register INTMSKCLR EMIFA Interrupt Mask Clear Register Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...

  • Page 164: Emifa Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.3 EMIFA Electrical Data/Timing Table 7-42. Timing Requirements for AECLKIN for EMIFA Cycle time, AECLKIN c(EKI) Pulse duration, AECLKIN high w(EKIH) Pulse duration, AECLKIN low w(EKIL) Transition time, AECLKIN...

  • Page 165: Asynchronous Memory Timing

    (see Figure PARAMETER MAX and V (see Figure 7-33 Figure 7-34) C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7-32) -720 -850 A-1000/-1000 -1200 E - 0.7 E + 0.7 EH - 0.7 EH + 0.7...
  • Page 166 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module Output setup time, select signals valid to AAOE low osu(SELV-AOEL) Output hold time, AAOE high to select signals invalid...
  • Page 167 Strobe = 4 Byte Enables Address Write Data DEASSERTED Strobe Extended Strobe ASSERTED DEASSERTED Figure 7-35. AARDY Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Hold = 1 Strobe Hold = 2...

  • Page 168: Programmable Synchronous Interface Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.3.2 Programmable Synchronous Interface Timing Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module Setup time, read AEDx valid before AECLKOUT high su(EDV-EKOH) Hold time, read AEDx valid after AECLKOUT high h(EKOH-EDV) Table 7-47.
  • Page 169 Figure 7-37. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 READ latency = 2 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...
  • Page 170 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE AAOE/ASOE AAWE/ASWE A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn): − Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency −...

  • Page 171: Hold/Holda Timing

    Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (1) (2) (see Figure PARAMETER External Requestor Owns Bus C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP (see Figure 7-39) -720 -850 A-1000/-1000 UNIT -1200 7-39)

  • Page 172: Busreq Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.5 BUSREQ Timing Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles Delay time, AECLKOUT high to ABUSREQ valid d(AEKOH-ABUSRV) AECLKOUTx ABUSREQ C64x+ Peripheral Information and Electrical Specifications...

  • Page 173: I2C Peripheral

    Figure 7-41 is a block diagram of the I2C module. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C bus) specification version 2.1 and connected by C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...
  • Page 174 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 I2C Module Noise I2C Clock Filter Noise I2C Data Filter Shading denotes control/status registers. C64x+ Peripheral Information and Electrical Specifications Clock Prescale Peripheral Clock (CPU/6) I2CPSC Bit Clock...

  • Page 175: I2C Peripheral Register Description(S)

    I2C prescaler register ICPID1 I2C peripheral identification register 1 [Value: 0x0000 0105] ICPID2 I2C peripheral identification register 2 [Value: 0x0000 0005] Reserved Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...

  • Page 176: I2C Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.11.3 I2C Electrical Data/Timing 7.11.3.1 Inter-Integrated Circuits (I2C) Timing Table 7-52. Timing Requirements for I2C Timings Cycle time, SCL c(SCL) Setup time, SCL high before SDA low (for a...
  • Page 177 = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Repeated Start Figure 7-42. I2C Receive Timings STANDARD MODE C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Stop (see Figure 7-43) -720 -850 A-1000/-1000 -1200...
  • Page 178 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Stop Start Repeated Stop Start Figure 7-43. I2C Transmit Timings C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 179: Host-Port Interface (Hpi) Peripheral

    (Write) HPIA HPI address register (Read) Reserved Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 COMMENTS The CPU has read/write access to the PWREMU_MGMT register; the Host does not have any access to this register.

  • Page 180: Hpi Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.12.3 HPI Electrical Data/Timing Table 7-55. Timing Requirements for Host-Port Interface Cycles Setup time, HAS low before HSTROBE low su(HASL-HSTBL) Hold time, HAS low after HSTROBE low...
  • Page 181 Case 2. HPID read with auto-increment and read FIFO initially empty Case 1. HPIA write Case 2. HPID write with no auto-increment C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP (1) (2) 7-51) -720 -850 A-1000/-1000 -1200 9 * M + 20...
  • Page 182 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
  • Page 183 HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-45. HPI16 Read Timing (HAS Used) Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 184 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
  • Page 185 HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-47. HPI16 Write Timing (HAS Used) Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 186 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HAS (input) HCNTL[1:0] (input) HR/W (input) HSTROBE (input) HCS (input) HD[31:0] (output) HRDY (output) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
  • Page 187 , HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 w(HSTBH) mode. Figure 7-49. HPI32 Read Timing (HAS Used) Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP...
  • Page 188 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HAS (input) HCNTL[1:0] (input) HR/W (input) HSTROBE (input) HCS (input) HD[31:0] (input) HRDY (output) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
  • Page 189 , HSTROBE high pulse duration, must be met between consecutive HPI accesses in HPI32 w(HSTBH) mode. Figure 7-51. HPI32 Write Timing (HAS Used) Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...

  • Page 190: Multichannel Buffered Serial Port (Mcbsp)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.13 Multichannel Buffered Serial Port (McBSP) The McBSP provides these functions: Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit...

  • Page 191: Mcbsp Device-Specific Information

    Register 3 Partition G/H McBSP0 Enhanced Transmit Channel Enable XCERE30 Register 3 Partition G/H Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure COMMENTS The CPU and EDMA3 controller can only read this register;...
  • Page 192 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HEX ADDRESS RANGE ACRONYM 0290 0000 3400 0000 0290 0004 3400 0010 0290 0008 0290 000C 0290 0010 0290 0014 0290 0018 0290 001C 0290 0020 0290 0024...

  • Page 193: Mcbsp Electrical Data/Timing

    CLKX int CLKX ext CLKX int CLKX ext (see Figure 7-52) PARAMETER CLKR/X int C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (see Figure 7-52) -720 -850 A-1000/-1000 -1200 (2) (3) 6P or 10 0.5t...
  • Page 194 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP Pulse duration, CLKR/X high or CLKR/X low w(CKRX) Delay time, CLKR high to internal FSR valid d(CKRH-FRV)
  • Page 195 FIXED-POINT DIGITAL SIGNAL PROCESSOR Bit(n-1) Bit 0 Bit(n-1) Figure 7-52. McBSP Timing Figure 7-53. FSR Timing When GSYNC = 1 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (n-2) (n-3) (n-2) (n-3) Figure...
  • Page 196 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Setup time, DR valid before CLKX low su(DRV-CKXL) Hold time, DR valid after CLKX low h(CKXL-DRV) (1) P = 1/CPU clock frequency in ns.
  • Page 197 T – 2 T + 3 –2 –2 H – 2 H + 4 Bit(n-1) (n-2) Bit(n-1) (n-2) C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP (1) (2) -720 -850 UNIT -1200 SLAVE 2 – 18P 5 + 36P 7-55) -720...
  • Page 198 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Setup time, DR valid before CLKX high su(DRV-CKXH) Hold time, DR valid after CLKX high h(CKXH-DRV) (1) P = 1/CPU clock frequency in ns.
  • Page 199 MASTER H – 2 T – 2 –2 –2 L – 2 Bit(n-1) Bit(n-1) C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 -720 -850 A-1000/-1000 -1200 MASTER SLAVE 2 – 18P 5 + 36P...

  • Page 200: Ethernet Mac (Emac)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14 Ethernet MAC (EMAC) The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6455 DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

  • Page 201: Emac Device-Specific Information

    RMII modes on the EMAC. For a detailed description of these pin functions, see Functions. Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70 shows which multiplexed pins are used in the MII, GMII, C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Table 2-3, Terminal...
  • Page 202 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER Using the RMII Mode of the EMAC The Ethernet Media Access Controller (EMAC) contains logic that allows it to communicate using the Reduced Media Independent Interface (RMII) protocol.
  • Page 203 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode. When the EMAC is enabled with these modes, the input clock to the PLL2 Controller (CLKIN2) must have a 25-MHz frequency.

  • Page 204: Emac Peripheral Register Description(S)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.2 EMAC Peripheral Register Description(s) Table 7-71. Ethernet MAC (EMAC) Control Registers HEX ADDRESS RANGE 02C8 0000 02C8 0004 02C8 0008 02C8 000F 02C8 0010 02C8 0014...
  • Page 205 Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) TX0CP Register Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) TX1CP Register Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) TX2CP Register C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008...
  • Page 206 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE 02C8 064C 02C8 0650 02C8 0654 02C8 0658 02C8 065C 02C8 0660 02C8 0664 02C8 0668...
  • Page 207 EMAC Control Module Interrupt Control Register EWINTTCNT EMAC Control Module Interrupt Timer Count Register Reserved Table 7-74. EMAC Descriptor Memory ACRONYM EMAC Descriptor Memory C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME DESCRIPTION...

  • Page 208: Emac Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.3 EMAC Electrical Data/Timing 7.14.3.1 EMAC MII and GMII Electrical Data/Timing Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see Cycle time, MRCLK c(MRCLK)
  • Page 209 Figure 7-62. EMAC Receive Interface Timing [MII and GMII Operation] Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Operation (see Figure 7-61) 1000 Mbps C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP -720 -850 A-1000/-1000 UNIT -1200 1000 Mbps (see Figure...
  • Page 210 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-79. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Delay time, MTCLK high to transmit selected signals valid d(MTCLKH-MTXD) (1) For MII, Transmit selected signals include: MTXD[3:0] and MTXEN. For GMII, Transmit selected signals include: GMTXD[7:0] and MTXEN.

  • Page 211: Emac Rmii Electrical Data/Timing

    FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 PARAMETER Figure 7-65. RMREFCLK Timing 10/100 Mbit/s (see Figure 7-66) PARAMETER C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Figure 7-65) -720 -850 A-1000/-1000 UNIT -1200 -720 -850 A-1000/-1000...
  • Page 212 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps Setup time, receive selected signals valid before MREFCLK (at DSP) su(MRXD-MREFCLK) high/low Hold time, receive selected signals valid after MREFCLK (at DSP) high/low h(MREFCLK-MRXD) (1) For RMII, receive selected signals include: MRXD[1:0], MRXER, and MCRSDV.

  • Page 213: Emac Rgmii Electrical Data/Timing

    1000 Mbps 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP -720 -850 A-1000/-1000 UNIT -1200 8 - 0.8 8 + 0.8 0.75 Figure 7-69)
  • Page 214 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps Setup time, receive selected signals valid before RXC (at DSP) high/low su(RXD-RXCH) Hold time, receive selected signals valid after RXC (at DSP) high/low h(RXCH-RXD) (1) For RGMII, receive selected signals include: RXD[3:0] and RXCTL.
  • Page 215 FIXED-POINT DIGITAL SIGNAL PROCESSOR Transmit (see Figure 7-70) PARAMETER 1st Half-byte 2nd Half-byte TXEN TXERR C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 -720 -850 A-1000/-1000 -1200 TXC at DSP pins Internal TXC (A)(B) UNIT...

  • Page 216: Management Data Input/Output (Mdio)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.4 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.

  • Page 217: Mdio Electrical Data/Timing

    FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-71. MDIO Input Timing (see Figure 7-72) PARAMETER Figure 7-72. MDIO Output Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Figure 7-71) -720 -850 A-1000/-1000 UNIT -1200 -720...

  • Page 218: Timers

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.15 Timers The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA3 channel controller. 7.15.1 Timers Device-Specific Information The C6455 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured as a general-purpose timer or a watchdog timer.

  • Page 219: Timers Electrical Data/Timing

    TINPLx TOUTLx Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR (see Figure 7-73) PARAMETER Figure 7-73. Timer Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (see Figure 7-73) -720 -850 A-1000/-1000 -1200 -720...

  • Page 220: Enhanced Viterbi-Decoder Coprocessor (Vcp2)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2) that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-4 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels.

  • Page 221: Enhanced Turbo Decoder Coprocessor (Tcp2)

    FIXED-POINT DIGITAL SIGNAL PROCESSOR Table 7-96. VCP2 Registers (continued) ACRONYM Branch Metrics State Metric TBHD Traceback Hard Decision TBSD Traceback Soft Decision Decoded Bits C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...

  • Page 222: Tcp2 Peripheral Register Description(S)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17.2 TCP2 Peripheral Register Description(s) EDMA BUS CONFIGURATION BUS HEX ADDRESS RANGE HEX ADDRESS RANGE 5000 0000 5000 0004 5000 0008 5000 000C 5000 0010 5000 0014...

  • Page 223: Peripheral Component Interconnect (Pci)

    Section Section Table 7-98. Default Values for PCI Configuration Registers REGISTER NOTE C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3, Device Configuration. Table 7-98 shows the registers which can DEFAULT VALUE 104C B000h...

  • Page 224: Pci Peripheral Register Description(S)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.18.2 PCI Peripheral Register Description(s) PCI HOST ACCESS HEX ADDRESS OFFSET 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 - 0x2B 0x2C 0x30 0x34...
  • Page 225 PCI Base Address Register 5 Mirror Register Reserved PCIMCFGDAT PCI Master Configuration/IO Access Data Register PCIMCFGADR PCI Master Configuration/IO Access Address Register C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 DSP ACCESS REGISTER NAME...
  • Page 226 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers (continued) DSP ACCESS HEX ADDRESS RANGE 02C0 0308 02C0 030C - 02C0 030F 02C0 0310 Table 7-101. DSP-to_PCI Address Translation Registers...
  • Page 227 PCI Master Window 10 PCI Master Window 11 PCI Master Window 12 PCI Master Window 13 PCI Master Window 14 PCI Master Window 15 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 228 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-103. PCI External Memory Space (continued) HEX ADDRESS OFFSET 4800 0000 - 487F FFFF 4880 0000 - 48FF FFFF 4900 0000 - 497F FFFF 4980 0000 - 49FF FFFF...

  • Page 229: Pci Electrical Data/Timing

    7.18.3 PCI Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specification (version 2.3). The AC timing specifications are not reproduced here. For more information on the AC timing specifications, see section 4.2.3, Timing Specification (33 MHz timing), and section 7.6.4, Timing...

  • Page 230: Utopia

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8 Bit Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is serviced directly by the EDMA3 controller.

  • Page 231: Utopia Electrical Data/Timing

    SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (see MAX and V MIN. Figure 7-74. UXCLK Timing (see MAX and V MIN. Figure 7-75. URCLK Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Figure 7-74) -720 -850 A-1000/-1000 UNIT -1200 0.4t 0.6t...
  • Page 232 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-108. Timing Requirements for UTOPIA Slave Transmit (see Setup time, UXADDR valid before UXCLK high su(UXAV-UXCH) Hold time, UXADDR valid after UXCLK high h(UXCH-UXAV) Setup time, UXENB low before UXCLK high...
  • Page 233 Figure 7-77. UTOPIA Slave Receive Timing Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Receive Cycles (see Figure 7-77) PARAMETER 0x1F C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP Figure 7-77) -720 -850 A-1000/-1000 UNIT -1200 -720 -850...

  • Page 234: Serial Rapidio (Srio) Port

    I/O buffer information specification (IBIS) models. For the C6455 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two DSPs connected via a 4x SRIO link directly to the user. TI has performed the simulation and system characterization to ensure all SRIO interface timings in this solution are met.
  • Page 235 DOORBELL Interrupt Condition Clear Register 0 Reserved RIO_DOORBELL1_ICSR DOORBELL Interrupt Condition Status Register 1 Reserved RIO_DOORBELL1_ICCR DOORBELL Interrupt Condition Clear Register 1 Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 236 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE 02D0 0220 02D0 0224 02D0 0228 02D0 022C 02D0 0230 02D0 0234 02D0 0238 02D0 023C 02D0 0240...
  • Page 237 LSU3 Control Register 3 RIO_LSU3_REG4 LSU3 Control Register 4 RIO_LSU3_REG5 LSU3 Control Register 5 RIO_LSU3_REG6 LSU3 Control Register 6 LSU3 Congestion Control Flow Mask Register C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 238 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE 02D0 0460 02D0 0464 02D0 0468 02D0 046C 02D0 0470 02D0 0474 02D0 0478 02D0 047C RIO_LSU4_FLOW_MASKS3 02D0 0480 - 02D0 04FC...
  • Page 239 Transmit CPPI Weighted Round Robin Control Register 1 RIO_TX_QUEUE_CNTL2 Transmit CPPI Weighted Round Robin Control Register 2 RIO_TX_QUEUE_CNTL3 Transmit CPPI Weighted Round Robin Control Register 3 C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 240 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE 02D0 07F0 - 02D0 07FC 02D0 0800 02D0 0804 02D0 0808 02D0 080C 02D0 0810 02D0 0814 02D0 0818...
  • Page 241 RIO_PE_FEAT Processing Element Features CAR Reserved RIO_SRC_OP Source Operations CAR RIO_DEST_OP Destination Operations CAR Reserved RIO_PE_LL_CTL Processing Element Logical Layer Control CSR Reserved C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...
  • Page 242 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE 02D0 1058 02D0 105C 02D0 1060 02D0 1064 02D0 1068 RIO_HOST_BASE_ID_LOCK 02D0 106C 02D0 1070 - 02D0 10FC...
  • Page 243 Port 3 Packet/Control Symbol Error Capture CSR 3 Port 3 Packet/Control Symbol Error Capture CSR 4 Reserved RIO_SP3_ERR_RATE Port 3 Error Rate CSR RIO_SP3_ERR_THRESH Port 3 Error Rate Threshold CSR C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 REGISTER NAME...

  • Page 244: Serial Rapidio Electrical Data/Timing

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE 02D0 2130 - 02D1 0FFC 02D1 1000 - 02D1 1FFC 02D1 2000 RIO_SP_IP_DISCOVERY_TIMER 02D1 2004 02D1 2008 02D1 200C...
  • Page 245 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report. Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications...

  • Page 246: General-Purpose Input/Output (Gpio)

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.21 General-Purpose Input/Output (GPIO) 7.21.1 GPIO Device-Specific Information On the C6455 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the UTOPIA, PCI, and McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral configuration and the C6455 device pin muxing, see 7.21.2 GPIO Peripheral Register Description(s)

  • Page 247: Gpio Electrical Data/Timing

    Submit Documentation Feedback FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 (1) (2) (see Figure 7-78) PARAMETER Figure 7-78. GPIO Port Timing C64x+ Peripheral Information and Electrical Specifications SM320C6455-EP (see Figure 7-78) -720 -850 A-1000/-1000 UNIT -1200 -720...

  • Page 248: Emulation Features And Capability

    SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET) The C6455 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides...

  • Page 249: Ieee 1149.1 Jtag

    TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.

  • Page 250: Revision History

    This data sheet revision history highlights the technical changes made to the SPRS276G device-specific data sheet to make it an SPRS276H revision. Scope: Applicable updates to the C64x device family, specifically relating to the SM320C6455-EP device, have been incorporated. Global Added 1.2-GHz device information...

  • Page 251: Mechanical Data

    The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. Submit Documentation Feedback SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1.45...

  • Page 252: Packaging Information

    www.ti.com PACKAGING INFORMATION Orderable Device Status SM320C6455BGTZEP ACTIVE SM320C6455BGTZSEP ACTIVE V62/07649-01XA ACTIVE V62/07649-02XA ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.

  • Page 254: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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