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Texas Instruments DM38x DaVinci User Manual

Digital media processor high-definition video processing subsystem (hdvpss)

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DM38x DaVinci™

Digital Media Processor

High-Definition Video Processing Subsystem

(HDVPSS)

User's Guide

Literature Number: SPRUHI7A

December 2012 – Revised June 2016

Table of Contents

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Page 1 DM38x DaVinci™ Digital Media Processor High-Definition Video Processing Subsystem (HDVPSS) User's Guide Literature Number: SPRUHI7A December 2012 – Revised June 2016...
Page 2: Table Of Contents
HD_VENC_D Registers ..................1.3.10 NOISE_FILTER Registers ....................1.3.11 SC_M Registers ................... 1.3.12 SD_VENC Registers ....................1.3.13 VCOMP Registers ..................1.3.14 VIP_PARSER Registers Contents SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 3 1-44. Input I/F Vertical Timing ......................1-45. Input Data Timing ....................1-46. Interrupt Horizontal Timing ....................1-47. Interrupt Vertical Timing SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 4 1-95. 4-Pin Reduced ACTVID Signaling with Vertical Ancillary Data ..........1-96. 4-Pin Reduced ACTVID Signaling with No Vertical Ancillary Data List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 5 ..................... 1-143. Peaking Filter at fs/4 ..................1-144. Vertical Scaler Block Diagram ................1-145. Mixed 2-tap and 5-tap vertical interpolation SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 6 1-191. ARGB24-6666 (Data Type 5) ....................1-192. RGB24-888 (Data Type 6) ................... 1-193. ARGB32-8888 (Data Type 7) ................... 1-194. RGBA24-6666 (Data Type 8) List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 7 ..................... 1-239. CSC_csc03 Register ..................... 1-240. CSC_csc04 Register ..................... 1-241. CSC_csc05 Register ......................1-242. dei_reg0 Register ......................1-243. dei_reg1 Register SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 8 .................... 1-288. intc_intr3_ena_set1 Register ..................... 1-289. intc_intr3_ena_clr0 Register ..................... 1-290. intc_intr3_ena_clr1 Register ......................1-291. intc_eoi Register ....................... 1-292. clkc_clken Register List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 9 ................1-337. VPDMA_int1_channel2_int_stat Register ................1-338. VPDMA_int1_channel2_int_mask Register ................1-339. VPDMA_int1_channel3_int_stat Register ................1-340. VPDMA_int1_channel3_int_mask Register ................1-341. VPDMA_int1_channel4_int_stat Register SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 10 ................1-386. VPDMA_int3_channel6_int_mask Register ................1-387. VPDMA_int3_client0_int_stat Register ................1-388. VPDMA_int3_client0_int_mask Register ................1-389. VPDMA_int3_client1_int_stat Register ................1-390. VPDMA_int3_client1_int_mask Register List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 11 ................... 1-435. VPDMA_vip2_anc_a_cstat Register ................... 1-436. VPDMA_vip2_anc_b_cstat Register .................... 1-437. HD_VENC_D_cfg0 Register .................... 1-438. HD_VENC_D_cfg1 Register .................... 1-439. HD_VENC_D_cfg2 Register SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 12 ....................1-484. SC_M_cfg_sc11 Register ....................1-485. SC_M_cfg_sc12 Register ....................1-486. SC_M_cfg_sc13 Register ....................1-487. SC_M_cfg_sc17 Register ....................1-488. SC_M_cfg_sc18 Register List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 13 ....................1-533. SD_VENC_ylpf0 Register ....................1-534. SD_VENC_ylpf1 Register ....................1-535. SD_VENC_clpf0 Register ....................1-536. SD_VENC_clpf1 Register ....................1-537. SD_VENC_upf0 Register SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 14 ..............1-582. VIP_PARSER_output_port_a_src7_size Register ..............1-583. VIP_PARSER_output_port_a_src8_size Register ..............1-584. VIP_PARSER_output_port_a_src9_size Register ..............1-585. VIP_PARSER_output_port_a_src10_size Register ..............1-586. VIP_PARSER_output_port_a_src11_size Register List of Figures SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 15 .................. 1-614. VIP_PARSER_xtra3_port_b Register .................. 1-615. VIP_PARSER_xtra4_port_b Register .................. 1-616. VIP_PARSER_xtra5_port_b Register .................. 1-617. VIP_PARSER_xtra6_port_a Register .................. 1-618. VIP_PARSER_xtra7_port_b Register SPRUHI7A – December 2012 – Revised June 2016 List of Figures Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 16 1-44. Display Ports and VENC Names ....................1-45. OSD Interface Signals ......................1-46. DVO Formats ..................1-47. Definition of SAV and EAV words List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 17 ............... 1-95. Change Client Interrupt Field Descriptions (Word - 1) ............... 1-96. Change Client Interrupt Field Descriptions (Word - 2) SPRUHI7A – December 2012 – Revised June 2016 List of Tables Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 18 1-142. COMP_sd_settings Register Field Descriptions ............1-143. COMP_back_color_settings Register Field Descriptions ......................1-144. CSC REGISTERS ................1-145. CSC_csc00 Register Field Descriptions List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 19 1-191. intc_intr2_ena_set1 Register Field Descriptions ..............1-192. intc_intr2_ena_clr0 Register Field Descriptions ..............1-193. intc_intr2_ena_clr1 Register Field Descriptions ..............1-194. intc_intr3_status_raw0 Register Field Descriptions SPRUHI7A – December 2012 – Revised June 2016 List of Tables Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 20 1-240. VPDMA_int0_client0_int_mask Register Field Descriptions ............1-241. VPDMA_int0_client1_int_stat Register Field Descriptions ............1-242. VPDMA_int0_client1_int_mask Register Field Descriptions ............. 1-243. VPDMA_int0_list0_int_stat Register Field Descriptions List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 21 1-289. VPDMA_int3_channel2_int_stat Register Field Descriptions ............. 1-290. VPDMA_int3_channel2_int_mask Register Field Descriptions ............1-291. VPDMA_int3_channel3_int_stat Register Field Descriptions ............. 1-292. VPDMA_int3_channel3_int_mask Register Field Descriptions SPRUHI7A – December 2012 – Revised June 2016 List of Tables Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 22 1-338. VPDMA_vbi_sdvenc_cstat Register Field Descriptions ..............1-339. VPDMA_vpi_ctl_cstat Register Field Descriptions ............1-340. VPDMA_hdmi_wrbk_out_cstat Register Field Descriptions ............1-341. VPDMA_trans1_chroma_cstat Register Field Descriptions List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 23 1-387. nf_reg9 Register Field Descriptions ...................... 1-388. SC_M REGISTERS ................1-389. SC_M_cfg_sc0 Register Field Descriptions ................1-390. SC_M_cfg_sc1 Register Field Descriptions SPRUHI7A – December 2012 – Revised June 2016 List of Tables Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 24 1-436. SD_VENC_cvbs1 Register Field Descriptions ................ 1-437. SD_VENC_ccsc0 Register Field Descriptions ................ 1-438. SD_VENC_ccsc1 Register Field Descriptions ................ 1-439. SD_VENC_ccsc2 Register Field Descriptions List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 25 1-485. VIP_PARSER_xtra_port_b Register Field Descriptions ..............1-486. VIP_PARSER_fiq_mask Register Field Descriptions ..............1-487. VIP_PARSER_fiq_clear Register Field Descriptions ............... 1-488. VIP_PARSER_fiq_status Register Field Descriptions SPRUHI7A – December 2012 – Revised June 2016 List of Tables Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 26 1-533. VIP_PARSER_xtra4_port_b Register Field Descriptions ............1-534. VIP_PARSER_xtra5_port_b Register Field Descriptions ............1-535. VIP_PARSER_xtra6_port_a Register Field Descriptions ............1-536. VIP_PARSER_xtra7_port_b Register Field Descriptions List of Tables SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 27: Preface
TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. DaVinci, E2E are trademarks of Texas Instruments.
Page 28: High-Definition Video Processing Subsystem (Hdvpss)
High-Definition Video Processing Subsystem (HDVPSS) ........................... Topic Page ................Description of the Subsystem ....................Internal Modules ......................Registers High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 29: Description Of The Subsystem
Single Buffer: ARGB, 24 bit/pixel ARGB32 ARGB32 Single Buffer: ARGB, 32 bit/pixel Bitmap Bitmap Single Buffer: Color Lookup Table (RGB input only) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 30: 1.1.3 Features
Scaling of individual regions within a graphics layer will be supported. A scaled region will not overlap with another region • Supported graphics formats are: – 32-bit: ARGB8888 – 24-bit: RGB888 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 31 • Uses 59.94Hz output frame rate for both 59.94 and 60Hz source materials to maintain the same output SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 32 The HDVPSS supports two additional video input source in 420 or 422 tiled format (same as input for main and auxiliary video paths). This path can be used for both video transcode operations (utilizing a High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 33 Pins with VOUT1 are connected to DVO1 There is no need for any pinmux configuration for analog outputs. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 34 Submodule GRPX0 is controlled by registers GRPX1 • Submodule GRPX1 is controlled by registers GRPX2 • Submodule GRPX2 is controlled by registers GRPX3 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 35: 1.1.4 Functional Operation
Note that VPDMA only supports 422 paths for display only. In addition, the numbers shown on the VPDMA ports correspond to those listed in Table 1-3. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 36: Primary Input Path (Pri) Detailed Block Diagram
420 Current 420 N-1 420 N-2 10x4 10x4 10x4 CHR_US CHR_US CHR_US {[8], 2’d0} VIP0 Subsystem SC_M YUV422 Compositor High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 37: Auxiliary Input Path Detailed Block Diagram
CLKC VIN0/2 Data Path Register. The output of the Video Input Port drives the VPDMA module, which sends the resulting video to SDRAM. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 38: Vip Subsystem Detailed Block Diagram
2 3 1 0 2 3 1 0/1 3 4/5/6/7 multi_channel_select} multi_channel_select} VBI A VBI B Y_LO[15:0] UV_LO[15:0] Y_UP[15:0] UV_UP[15:0] High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 39 DMA transfer to pull in the portion of the list that it can store in the internal VPDMA memory. The List Manager will sequentially process descriptor in the list and performs the data transfers. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 40: 1.1.5 Hdvpss Data Flow
The color space converters (CSC_VIP0 and CSC_VIP1) within the VIP subsystem receive data from one of five sources: • VIP_PARSER PortA Output (422) • VIP_PARSER PortB Output (422) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 41 VENC or standard-definition VENC. The input to this scaler can come from 1 of 6 sources: the output of the video compositor, the composited HDMI output, one of the two bypass-422 paths, or the secondary-1 input. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 42 422S data: • 422 semi-planar tiled/non-tiled (separate luma and chroma buffers). Cb/Cr interleaved in chroma buffer. 420T data: High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 43: 1.1.6 Example Data Flows
(DVO2) VENC_A VENC (DVO1) All types of RGB formats described in VPDMA section. VIN0 HDMI DVO1 DVO2 VIN1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 44: Hdvpss Mux Select Register
SD display. In this case, the three output displays are independent. The SC WRBK scaler will be used to scale the primary blended display and convert to interlaced format for the SD output. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 45: Hdvpss Tri Display Data Flow
SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 46: Hdvpss Tri Display Data Flow
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 47: Hdvpss Tri Display Dual Transcode
VENC_A VENC All types of RGB formats (DVO1) (DVO2) described in VPDMA section. VIP1 HDMI DVO1 DVO2 VIN1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 48: Hdvpss Mux Select Register
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 49: Hdvpss Tri Display Dual Transcode With Video Capture
VENC_A VENC (DVO1) (DVO2) All types of RGB formats described in VPDMA section. VIP1 HDMI DVO1 DVO2 VIN1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 50: Hdvpss Mux Select Register
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 51: Hdvpss Tri Display With Video Capture
(DVO2) VENC_A VENC All types of RGB formats (DVO1) described in VPDMA section. VIN0 HDMI DVO1 DVO2 VIN1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 52: Hdvpss Mux Select Register
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 53: Hdvpss Tri Display With Video Capture And Noise Filter
VENC_A VENC (DVO1) (DVO2) All types of RGB formats described in VPDMA section. VIP1 HDMI DVO1 DVO2 VIN1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 54: Hdvpss Mux Select Register
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 55: 1.1.7 Interrupt Mapping
Enable Mask Off Interrupt Interrupt Status Interrupt Status event MASK Raw/Set Enabled/Clear Disable Mask On Interrupt Interrupt Enable/Clear SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 56 The source of interrupts described at HDVPSS level come from Sub-Modules of HDVPSS like VPDMA, DEI, VIP0, etc. Figure 1-13 shows interrupt mapping from module level to HDVPSS level. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 57: Module To Hdvpss Interrupt Mapping Level
_raw dvo1_int1 (End of Vertical Blanking Interrupt) DVO1 vout1_int1 _raw dvo1_int2 (Start of Frame Interrupt) DVO1 vout1_int2 _raw SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 58: Module To Hdvpss Interrupt Mapping Level
COMP chr_ds_uv_err_int CHR_DS_NF nf_chr_ds_uv_err_int_raw chr_ds_uv_err_int CHR_DS0_VIP0 vin0_chr_ds_1_uv_err_int_raw chr_ds_uv_err_int CHR_DS1_VIP0 vin0_chr_ds_2_uv_err_int_raw CHR_DS0_VIP1 chr_ds_uv_err_int Vin1_chr_ds_1_uv_err_int_raw chr_ds_uv_err_int CHR_DS1_VIP1 Vin1_chr_ds_2_uv_err_int_raw High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 59: 1.1.8 Clocking
Clock Select (address: 0x48100114) register. Please make sure the required VENCs are enabled in the CLKC Video Encoder Enable (address: 0x48100118) register. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 60: 1.1.9 Reset
7. Reset all modules and Vencs by writing reset bits. 8. Request IDLE, on IDLE acknowledgement, clocks can be shut down. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 61: Internal Modules
Rom Filter is based on four anchor pixels representing a four tap filter. The general 4-tap filter Catmull- Rom filter is defined in Figure 1-17. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 62: Catmull-Rom Filter Definition
2/4=1/2. There are four half pels between Anchor1 and Anchor2. Midway is two pels, so x=2/4. Figure 1-19. Anchor Pixels Anchor0 Anchor1 x = 2/4 Anchor2 Anchor3 Chroma Luma Interpolated Chroma High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 63: Ideal 4:2:2 Chroma Upsampling For Interlaced Scan
Bottom Field Frame Field Chroma Luma Interpolated Chroma Following interpolation, the chroma samples lie on a 4:2:2 grid. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 64: Vpdma Modes Of Operation
2. For VPDMA chroma clients, Mode A is used for 420 data and Mode B is used for 422 data. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 65 CHR_US_reg3.interp_fid0_c2 = 0x00e8 CHR_US_reg3.interp_fid0_c3 = 0x3fe8 CHR_US_reg4 to CHR_US_reg7 are not used so their values are "don't care". SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 66: Color Space Converter (Csc)
Rd, Gd, Bd, and Yd will be in the range [64-940] • Cb and Cr will be in the range [64-960] • D = 4 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 67: Conversion From Rgb To Ycbcr
Figure 1-26. Conversion from YCbCr to RGB 1.1644 –0.0003 1.7927 –248 1.1644 –0.2132 –0.5329 1.1642 2.1125 –0.0001 –289 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 68: Quantized Coefficients Of Hdtv Application With Video Data Range
-0.0001 0x0000 D0(12-bit) 0x040 D0(12-bit) -248 -992 0xC20 D1(12-bit) 0x200 D1(12-bit) 0x134 D2(12-bit) 0x200 D2(12-bit) -289 -1156 0xB7C High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 69: Conversion From Rgb To Ycbcr
Conversion from YCbCr to RGB: Figure 1-28. Conversion from YCbCr to RGB –0.0003 1.3717 –176 –0.3365 –0.6984 1.7336 –0.0016 –222 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 70: Conversion From Rgb To Ycbcr
Figure 1-30. Conversion from YCbCr to RGB 1.1641 –0.0018 1.5958 –223 1.1641 –0.3914 –0.8135 1.1641 2.0178 –0.0012 –277 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 71: Conversion From Rgb To Ycbcr
-0.0012 0x1FFF D0(12-bit) 0x040 D0(12-bit) -223 -892 0xC84 D1(12-bit) 0x200 D1(12-bit) 0x220 D2(12-bit) 0x200 D2(12-bit) -277 -1108 0xBAC SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 72: 1.2.3 Compositor Module
480i, it cannot use either the main or PIP video inputs, and must use a different graphics input. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 73: Comp Module Block Diagram
Blender2 Blender3 Blenders HD main video HD main video (CIT) SD video HD pip video Grpx-0 Grpx-1 Grpx-2 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 74: Display Width And Height Parameters
Figure 1-32. Display Width and Height Parameters Display Width Background color (x, y) Input source width Display height High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 75 The alpha value for SD video is 0xFF. The priority level used SD video is set in: COMP→SD_setting.vid_order (irrespective of COMP→SD_setting.g_reorder bit-field value). SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 76: Blender Diagram
=(1-b)*input1+ (b)*input2 if input2 is top layer and input1 is bottom layer High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 77: Blending And Reordering
(g0_order, g1_order, g2_order bit-fields). Otherwise, graphics layers are reordered based on GRPX register (priority) settings as mentioned in the above sections. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 78: Alpha Blender Block Diagram
VPDMA configuration for any of the input channel. When underflow condition happens, the background color programmed in the COMP module is sent for the underflowed pixels. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 79: Constrained Image Generator (Cig)
Displaying aux video channel output directly on the HD_DVO2 output (Dual-Video Channel mode) The block diagram of CIG module is shown in Figure 1-36. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 80: Cig Block Diagram
The blending alpha value configured in CIG module is carried onto COMP module. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 81 Note that the chroma keying and alpha assignment for blending feature as well as output interlacing are still available even in the bypass mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 82: Graphics Module (Grpx)
3. Scalar configuration attributes (13 words) – configure scaler specific attributes (only required if scaling is enabled) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 83: Grpx Functional Block Diagram
Output Port Output Port COMP Figure 1-38. GRPX Output frame_width Region 0 Region_width (disp_pos_x, disp_pos_y) Region 1 Region 2 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 84: Frame Configuration Attribute (Configuration Descriptor Payload Word 0-3)
Soft reset Software reset of GRPX data pipeline: Writing 1 resets GRPX data pipeline Returns 0 on read always High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 85: Region Configuration Attribute (Inbound Data Descriptor Word 4-7)
101: Transparency enable 0 = Disable 1 = Enable transparency for video layer 127-104: Transparency color (RGB24) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 86 The minimum size of vertical region is one line, and no multiple regions on a same line is allowed (nor is possible) per “region” graphics definition. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 87: Region Display Position And Gap Requirement Illustration
Enabling of this feature requires “stenciling_en” bit- field to be set to `1`. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 88: Blending And Transparency Configuration
3. Stenciling application to force masked pixels (stencil data = 1) with alpha = 0 4. Scaling of Alpha (if scaling enabled) 5. Box Blending (force alpha = programmed box_blend_level) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 89: 1.2.5.2.4 Region Scaler Configuration Attributes
Coefficient for Horizontal TAP 2 Phase 0 Reserved [15:10] reserved coefh2_p1 [25:16] Coefficient for Horizontal TAP 2 Phase 1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 90: Region Scaler Attributes 3
Coefficient for Horizontal TAP 4 Phase 2 Reserved [47:42] Reserved coefh4_p3 [57:48] Coefficient for Horizontal TAP 4 Phase 3 Reserved [63:58] Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 91: Region Scaler Attributes 5
Coefficient for Vertical TAP 1 Phase 0 Reserved [15:10] reserved coefv1_p1 [25:16] Coefficient for Vertical TAP 1 Phase 1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 92: Region Scaler Attributes 8
Coefficient for Vertical TAP 3 Phase 2 Reserved [47:42] reserved coefv3_p3 [57:48] Coefficient for Vertical TAP 3 Phase 3 Reserved [63:58] reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 93: Region Scaler Attributes 10
VPDMA LIST. The configuration of descriptors is explained and illustrated in the VPDMA chapter. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 94: Standard-Definition Video Encoder (Sd_Venc)
– Programmable Color-burst Amplitude – Programmable Color Space Converter – Programmable Sub-carrier Frequency and SCH phase – Programmable Luma Delay High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 95: Venc Block Diagram
HIGH. Figure 1-41 provides an example of this synchronization operation. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 96: Example Of Multiple Venc Synchronization
Figure 1-42. Video Timing HITV HITV AV_H_STA Top Field AV_H_STA Active Video AV_H_STP Bottom Field AV_H_STP Progressive (ITLC=0) Interlace (ITLC=1) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 97: Input I/F Horizontal Timing
Base V Counter venc_dtv_hs DTV_HS_H_STA=0 DTV_HS_H_STP=4 venc_dtv_vs DTV_VS_H_STA=5 DTV_VS_H_STP=9 venc_dtv_fid DTV_FID_H_STA=8 venc_dtv_avid D718 D719 ygin/ubin/vrin 1 clk1x DTV_AVID_H_STA=242 DTV_AVID_H_STP=1682 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 98: Input I/F Vertical Timing
1 cycle clk2x rising edge latency from avid when phase 1x = 1 venc_dtv_avid ygin/ubin/vrin Active Video = DTV_AVID_H_STP-DTV_AVID_H_STA High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 99: Interrupt Horizontal Timing
Base FID venc_irq IRQ_V_STA=3 (1/2H) Base V Counter 522 523 524 bottom field Base FID venc_irq IRQ_V_STA=3 (1/2H) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 100: Tvdetgp Horizontal Timing
TVDETGP_V_STA=6 (1/2H) TVDETGP_V_STP=12 (1/2H) DVO V Counter 523 524 Bottom field DVO FID venc_tvdetgp TVDETGP_V_STA=6 (1/2H) TVDETGP_V_STP=12 (1/2H) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 101: Sdtv Horizontal Timing
H ref to H Blanking Start AV_H_STP HITV Equalizing Pulse Width 62 63 Serration Pulse Width 1/2H HITV/2 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 102: I Vertical Timing
616 617 618 619 620 621 622 623 V Counter bottom field 2.5H (SVSW=1) 2.5H 2.5H AV_V_STA1=45 (1/2H) AV_V_STP1=620 (1/2H) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 103: Sdtv Dac Video Output Pipeline Delay (Pxlr = 0)
Figure 1-54. SDTV DAC Video Output Pipeline Delay (PXLR = 1) clk2x Base H Counter DAC Video Output Sync 50% 63 clk TV H Counter TV V Counter SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 104: Non-Interlaced Format
262H Non-Interlace 263H Non-Interlace 262H, 263H Non- Interlace 1728 625i 312H Non-Interlace 313H Non-Interlace 312H, 313H Non- Interlace High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 105: Horizontal Blanking Shaping
0.5H position for the interlaced mode. If vdin is behind hdin assertion. Vertical reset is suspended until the next hdin rise edge or the next 0.5H for the interlaced mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 106: Interlaced Slave Vertical Timing (Fmd = 0,1)
Base V Counter bottom field Base FID 0.25H 0.25H hdin vdin Base V Counter top field Base FID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 107: Interlaced Slave Vertical Timing (Fmd = 3)
These four modes can be selected by the FMD register. Figure 1-62 shows the timing of each mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 108: Field Detection Mode
Figure 1-63. Field Detection by VD Phase (FMD=3) 0.5H 0.5H hdin 0.25H 0.25H Detected as “top” vdin 0.25H 0.25H Detected as “bottom” vdin High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 109: Color Bar Table
UPFC4 6/128 h(9), h(17) h(10), h(16) UPFC5 -20/128 h(11), h(15) h(12), h(14) UPFC6 78/128 h(13) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 110: Color Systems
TV formats such as PAL-M, PAL-60 and so on. Table 1-37. Color Systems Color System NTSC SECAM Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 111      The following are examples of CSC programming for various input and output combinations. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 112     − − 52 322     4095 1000 2089 × × 1400 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 113     − − 61 375     4095 1000 2089 × × 1400 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 114    4095 1000 92.5% 1932.6 × × × 1400 4095 1000 7.5% × × × 1400 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 115 ) 131( 100( 0.075 4095( ) 180 × × ) 131( Sync 4095( ) 958 × ) 131( SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 116: Luma Lpf Filter Coefficient
CLPFC0 h(1) h(9) CLPFC1 h(2) h(8) CLPFC2 h(3) h(7) CLPFC3 12/128 h(4) h(6) CLPFC4 32/128 h(5) CLPFC5 40/128 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 117: Cvbs Video Amplitude
The generic VBI-data is also inserted when used. The detail of the VBI-data insertion is described in Section 1.2.6.2.11. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 118: Sub-Carrier Increment Parameters
π  NTSC sin 2 cos 2 =  π ± π   sin 2 cos 2 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 119 Where D has a range of 0 to ±1117 and D has a range of 0 to ±1359. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 120: Limiter Configuration
0.506 CVLCLP 1024 128 2456 = − × × = − 0.35 CVUCLP 1024 128 1699 × × High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 121: Sub-Carrier Parameter Registers
Y and C to generate CVBS. The adjustable range is from –8 to 7 cycle of clk2x. S-Video Y is not affected. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 122: Wss_Data Register Usage
WSS_DATA and WSS_EN registers are exclusively used for WSS and CGMS insertion depending on the timing format. The amplitude of CGMS data is automatically determined as 70% of white (70IRE). High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 123 1.2.6.2.13 Register Setting for Various Video Standards Table 1-41 is a list of the typical register setting for various video standards. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 124: Vbi I/F Horizontal Timing
CVBS bottom field AV_V_STA1=34 (1/2H) AV_V_STP1=519 (1/2H) venc_vbi_req vbi_venc_val vbi_req acknowledged by vbi_if module venc_vbi_en High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 125: Typical Register Setting For Various Video Standards
2516 2516 2516 14391 2516 20632 Numerator Sub-carrier Increment SCP2 0x14C[31:16] 16875 16875 16875 16875 16875 21390 Denominator SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 126: Dac Output Select
DUPFC4 6/128 h(9), h(17) h(10), h(16) DUPFC5 -20/128 h(11), h(15) h(12), h(14) DUPFC6 78/128 h(13) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 127: Dac I/F Logic
DC output of DALVL D/A converted value. Figure 1-71. DAC I/F Logic DAxS CVBS DAIV DADC DAUPS DAOUT Oversampling DALVL SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 128: High-Definition Video Encoder (Hd_Venc)
Please check SD VENC userguide for details. HDCOMP Analog HD_VENC_A Not applicable All features in analog data flow path. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 129: Hd Venc Block Diagram
Note: The dtv_vs, dtv_vbi, dtv_hs and dtv_hbi signals are generated by the encoder but are not used by the HDVPSS design. Therefore, all parameters related to these signals do not need to be specified. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 130: Vertical Sync Signals For Osd
Line Related Sync Signals for OSD Interface hs_st_a nth Line (Pixels) (n+1)th Line hs_wth_a (n-1)th Line DTV_HS 4 Pixels ST_HBI DTV_HBI st_cap DTV_ACTVID act_pix High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 131: Video Data Interface Between Osd And Encoder
“Y_RGBn” in CFG0 register to select RGB or YCbCr color spaces. Figure 1-75. Video Data Interface Between OSD and Encoder CLK1X ACT_VID G/Y[ :0] B/Cb[ :0] R/Cr[ :0] SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 132: Osd Interface In Progressive Mode
Figure 1-76. OSD Interface in Progressive Mode OSD Interface in Progressive Mode Pixels OSD_AVST_H OSD_AVD_HW OSD_AVST_V1 DTV_FID Frame 0 DTV_VBI Frame 1 DTV_ACTVID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 133: Osd Interface In Interlace Mode
Figure 1-77. OSD Interface in Interlace Mode OSD Interface in Interlace Mode Pixels OSD_AVST_H OSD_AVD_HW OSD_AVST_V1 DTV_FID DTV_VBI Even Field OSD_AVST_V2 Odd Field DTV_ACTVID SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 134: Dvo Formats
000, XXX. All the possible values for XXX are listed in Table 1-47. Table 1-47. Definition of SAV and EAV words BITS SAV/EAV Function High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 135: Progressive Configuration Of Dvo
Figure 1-78. Progressive Configuration of DVO DVO in Progressive Mode Pixels DVO_AVST_H DVO_AVD_HW DVO_AVST_V1 Frame 0 DVO_VS Frame 1 DVO_ACTVID DVO_HS_WD DVO_HS_ST DVO_HS SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 136: Interlace Configuration Of Dvo
DVO in Interlace Mode Pixels DVO_AVST_H DVO_AVD_HW DVO_AVST_V1 DVO_FID Even Field DVO_VS OSD_AVST_V2 Odd Field DVO_ACTVID DVO_HS_WD DVO_HS_ST DVO_HS High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 137: Typical Vbi Data Package
The first VBI line will be used for type-A data packet of CEA-805-A standard or IEC-62375 standard. • The second VBI line will be used for type-B data packet of CEA-805-A standard SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 138: Programmable Capacity Of First Line Encoder
If CFG0.RD_MEM = ‘1’, processor can read and write these LUTs as regular memory. • If CFG0.RD_MEM = ‘0’, processor can only write to these LUTs as regular memory. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 139: Memory Map Addresses For Configuration Register And Lut Memories
3 × 3 matrix. See the Color Space Converter section for more details. The CSC module can be bypassed by setting CFG0.BYPS_CS bit-field to 1. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 140: 1.2.8 Vip Parser
A digital interface stream is based on analog video. The waveform for a line of NTSC analog video is shown in Figure 1-81. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 141: Ntsc Analog Video Waveform For One Horizontal Line
Such a multi-camera multiplex is useful in the digital security markets. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 142: Code Word Embedded Video Format
0, 1, 1 0, 0, 0 0, 0, 1 Active Field {x, y, z} = {F, V, H} Time High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 143: Planar Buffer Storage Description
Buffers X Active Field Vertical Ancillary Data time Buffer X+1 Active Video Y and CbCr Buffers X+1 Active Field SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 144: B Interface Discrete Sync Pixel Multiplexing
Figure 1-87. Figure 1-87. 16b Interface Discrete Sync Pixel Multiplexing Bit 15 Bit 0 time High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 145: Device Pins For Ports A And B
Port A vinX_pclk1 PIXCLK Data 0 vinX_hsync1 HSYNC Data 1 Data 7 vinX_vsync1 VSYNC vinX_de1 ACTVID Port B vinX_fld1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 146: Discrete Sync Signals
Likewise, VSYNC can be a strobe that is active one or more cycles and can deassert before the actual end of vertical blanking or VSYNC may be active for the full duration of vertical blanking. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 147: Type 1, First Horizontal Blanking Pixel
Other devices consider only video to be ACTIVE Video. Figure 1-92. Type 1, First Vertical Ancillary Data Pixel PIXCLK HSYNC VSYNC ACTVID DATA SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 148: Type 1, Horizontal Blanking In Video Region
Figure 1-94. Type 1, First Video Pixel PIXCLK HSYNC VSYNC ACTVID DATA High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 149: Pin Reduced Actvid Signaling With Vertical Ancillary Data
Figure 1-97. 4-Pin Reduced HSYNC Signaling with Vertical Ancillary Data Pixclk VSYNC HSYNC SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 150: Vsync Pre And Post Window
If VSYNC is high throughout the transition window, then the HSYNC line is in vertical blanking. If VSYNC is low throughout the transition window, then the HSYNC line is in active video. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 151: Vsync Equivalence When Using Transition Window
= ‘0’ defines a minimum size window which will capture the value of VSYNC on the same cycle that HSYNC goes active. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 152: Fid Registering When Using Hsync
HSYNC Y/UV FID Internally Registered Figure 1-101. FID Registering When Using ACTVID PIXCLK ACTVID Y/UV FID Internally Registered High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 153: Field Id Determination By Vsync Skew
1-54. Table 1-54. Polarity Table for FID Determination By VSYNC Skew Cfg_fid_polarity Transition in Pre/Post Range FID Determination SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 154: Example Of 525-Line Fid Determination By Vsync Skew
Also, the VSYNC transition window is not employed. VSYNC is captured at the first pixel of each ACTVID grouping of pixels. Lines are separated by ACTVID transitioning inactive. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 155: Horizontal Ancillary Data Packing When Hsync Used As Sync Signal
Ancillary Data Horizontal Vertical Blanking Ancillary Data Buffer Luma Field/Frame Buffer Active Field Chroma Field/Frame Buffer X bytes/line SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 156: Progressive Frame Vertical Blanking Ancillary Data Storage
10 bits (single pixel interface) or 20 bits (parallel Y-Cb/Cr interface) of data, only the 8 (single pixel interface) or 16 (parallel 8bY-8bCb/Cr interface) most significant bits of each pixel are used. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 157: Code Word Format Example Followed By Video Data
1-108. The input data mode is 8 bits for the example. Figure 1-108. Code Word Format Example Followed by Video Data 0xFF 0x00 0x00 Flags time SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 158: Error Correction Matrix
F, V, and H Flags 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 159: Embedded Sync Packing
Active Field X bytes/line Ancillary Data Ancillary Data Buffer Luma Frame Buffer Active Field Chroma Frame Buffer X bytes/line SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 160: Rgb Frame Storage
Vertical Blanking/ X Bytes/line Ancillary Data Field Ancillary Data Buffer Packed RGB Frame Buffer RGB Active Field X*3 bytes/line High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 161: 1.2.8.2.7.2 2-Way Multiplexing
However, the two streams are not necessarily sending the same pixel site in adjacent clock cycles. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 162: Example Of 4-Way Multiplexing
PAL while another one can be NTSC. A line is comprised of YUV422 pixels in repeating patterns of CbYCrY. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 163: Bit Line Mux Interface
SAV/EAV startcodes are always 0. Figure 1-115. 16-bit Line Mux Interface Luma Channel Channel Data Channel Data Chroma Channel Meta Data Tags SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 164: Bop/Eop Definition Of A Period
Figure 1-116. BOP/EOP Definition of a Period BOP=1, EOP=0 Vertical BOP=0, EOP=0 Blanking BOP=0, EOP=1 BOP=1, EOP=0 Active Field BOP=0, EOP=0 BOP=0, EOP=1 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 165: Ti Line Mux Mode Channel Id Remapping
The SrcIDx size status registers and the Source FID status registers reflect the remapped Channel ID when the port is in TI Line Mux mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 166: Channel Id Embedded In Eav/Sav
1-117. The maximum number of values defined by this 4-bit range is 2 = 16. However, only Channel IDs in the range {0:7} are supported. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 167: Channel Id Inserted Into Horizontal Blanking
Disconn Comple Complete ProtoVio ProtoVio ProtoVio ProtoVio PrtA OpPrtB OpPrtB OpPrtA OpPrtA InPrtB InPrtA PrtB PrtAV Conn Vdet SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 168: Vip Parser Interrupts
‘0.’ Otherwise, the hardware would not be able to set any subsequent interrupts of the same type. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 169 0xFE. If data[23:16]==0x00, the clipped value will be 0x01. Likewise, clipping is done for data bit ranges 15:8 and 7:0 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 170 Source Number that is cropped and sent to memory. The Vertical Ancillary Data Cropping region is described in Figure 1-118. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 171: Vertical Ancillary Data Cropping Region
USE_NUMPIX must be evenly divisible by 2. If the output of vip_parser is sent to a 4:2:2 to 4:2:0 converter, then USE_NUMLINES must also be evenly divisible by 2. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 172: Discrete Sync Interface Signals
1.2.8.2.5.1. In summary, choose one signal from Group 1 and one signal from Group 2. There should be a way to capture the external data. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 173: Vsync And Hblank Input Signals
Figure 1-122. vsync and hsync Input Signals vsync hsync SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 174: Vsync And Actvid Input Signals
Figure 1-124. vblank and hsync Input Signals vblank hsync High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 175: Vblank And Hblank Input Signals
Figure 1-126. vblank and actvid Input Signals vblank actvid SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 176: Line And Pixel Capture, Vblank And Hsync
Figure 1-128. Line and Pixel Capture, hsync hsync First Last Last First Line X-1 Line X Line X+1 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 177: Line And Pixel Capture, Actvid
In 8-bit mode, note that the 4:2:2 YUV input color component order is Cb, Y followed by Cr and Y. For 16 and 24-bit input modes, all the components are sent in the same cycle. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 178 13. Set yuv_srcnum_stop_immediately = 0x0000_0000 14. Set anc_srcnum_stop_immediately = 0x0000_0000 15. Set ENABLE = 1 16. Set CLR_ASYNC_FIFO_RD and CLR_ASYNC_FIFO_WR to 0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 179: 1.2.9 De-Interlacer (Dei) Module
Original Line Spatial Interpolation Input Data Field Motion Mixture Buffers Detection Temporal Interpolation New Line Film Mode Selector Detection SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 180 DEI supports four interpolation modes when converting interlaced pictures to progressive pictures. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 181 VPDMA is used to transfer the data in and out of DEI as shown in the following figure. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 182: Vpdma Transfer Ports
MVin_f1 (1-field delayed Motion Vectors) – Two field delay (N-2) • Yin_f2 (2-field delayed Luma) • UVin_f2 (2-field delayed Chroma) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 183: Auxiliary Data
– MVin_f1 • Outputs – MVout_f0 – Output Scalar Figure 1-132. Auxiliary Data Auxiliary Data DEI (4-field MDT mode) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 184: Module Interrupts
In any of these cases, the input video data is not matching what the deinterlacer programming is expecting. Software should reconfigure the deinterlacer to match the proper input video timing. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 185: Noise Filter (Nf)
32x32 tiles and process each of them independently. If the width or height of the frame is not a multiple of 32, 0x0s (for Luma) and 0x80s (for Chroma) will be padded into rightmost and/or bottommost tiles. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 186: Noise Filter Architecture Block Diagram
For U and V channels, this filtering needs to be performed only at even rows and even columns due to the 4:2:0 format. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 187: Motion Versus Blending Factor Function
IIR low pass filter as shown in the following example. Frame_noise_filtered=Frame_noise_previous* noise_IIR_coefficient +Frame_noise *(1- noise_IIR_coefficient ) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 188: Versus Totalframe_Noise Function
(firmware) frame_cntl Threshold cur_tile_y vpi_in cur_tile_uv filtered_tile_y vpi_in vpi_out ref_tile_y filtered_tile_uv filter_Tile vpi_in vpi_out ref_tile_uv vpi_in High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 189: Incomplete Boundary Tile Data Masking
In this case, the update should only be done at the beginning or end of the frame – once per frame. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 190: Nf Configuration For Each Basic Mode
DMA for reference frame reference frame nf_bypass_cfg b’00 b’00 b’00 b’01 (or b‘11) b’10 spatial_strength X 6 temporal_strength High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 191: Scaler (Sc)
Figure 1-139. High Level Block Diagram Scalar YCbCr YCbCr Output Input Config Coef Register Memory VPI Control Interface VPDMA SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 192: Sc Block Diagram
(such as black box/curtains/noisy line-21 video) without modifying the VPDMA parameters. Figure 1-141. Input Image Trimming orgW offW srcW High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 193: Filter Implementation And Parameter Description
SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 194: Peaking Filter At
Figure 1-144. Vertical Scaler Block Diagram use_rav Polyphase YCbCr Scaler YCbCr Running Average Downscaler High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 195: Mixed 2-Tap And 5-Tap Vertical Interpolation
Initializations of accumulators affect the weights. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 196: Vertical Scaler Configuration Parameters
32 phases × 5 taps × 13 bits array (dependent on coefficients scale factor) Note: Bi-linear scaler is not present in this device. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 197: Horizontal Scaler Block Diagram
Figure 1-147. Horizontal Scaler Block Diagram YCbCr 1/2x Decimator 1/2x Decimator YCbCr Polyphase Scaler HS Coef Mem 32 phase x 7tap SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 198: Polyphase Filtering Example
1 4/8 acc=0; for tar_col=0:tarW-1 2 4/8 src_col=floor(acc); //simple example of nearest source mapping tarY[tar_col]=srcY[src_col]; 3 4/8 acc=acc+acc_inc; High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 199: Non-Linear Scaling Example
= K * (tar col) nlin_acc_inc = 2*a = 2*K K = left src inner col / (left tar inner col) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 200: Horizontal Scaler Related Parameter Configuration
1/4 < and < 1/2 By 2 By 2 1/2 < and < 1 Bypassed Bypassed > 1 Bypassed High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 201: Horizontal Polyphase Filter Related Parameter Configuration
Note: Source width and height variables for the polyphase filter are internally set with trimmer and decimation filter adjusted values. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 202: Sram Layout For 7Tap Coefficient
Figure 1-151. Figure 1-151. SRAM Layout for 5tap Coefficient Phase 0 Phase 31 C221 C220 C219 C218 C217 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 203: Vpi Control I/F Coef Data Format (7Tap)
VS Ver Chroma VS Ver Chroma VS Top / Bottom Luma VS Top / Bottom Chroma (a) sc_h (b) sc_m SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 204: Vpi Control I/F Memory Map (Read)
Care must be given to the order of the DMA descriptors so that blocking of VPI control bus does not occur. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 205: Coefficient Data Files
#---------------------------------------------------------- # read config file to get srcH/tarH/interlace_i/interlace_o #---------------------------------------------------------- open(INFILE, "<$cfg_file") or die "### ERROR: Cannot open $cfg_file"; SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 206 } elsif ( ($tarWi == ($srcWi>>1)) || ($tarWi == ($srcWi>>2)) ) { $hsc_file0 = "ppfcoef_scale_eq_1_32_phases_flip.dat"; } else { High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 207 $coef=join("",@coef); print "$coef\n"; close(INFILE); SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 208 // NonLinear Coring Function typical values // ---------------------------------------------------------------- NL_coring_thr NL_limit = 200; NL_lo_slope NL_hi_thr = 400; NL_hi_slope_shift = High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 209 = 0; if((interlace_in == 0) && (interlace_out == 1)) scale = double(2*tarH)/double(srcH); else scale = double(tarH)/double(srcH); sc_factor_rav = int(1024.0*scale+0.5); SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 210 = 0; hp_bypass = 0; if (srcWi==srcW) linear = 1; else linear = 0; // hor scaler parameters High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 211 // ========================================================================================== // Bypass Determination // ========================================================================================== // bypass if ((srcW==tarW)&&(srcWi==tarWi)&&(mod_srcH==mod_tarH)) sc_bypass = 1; else sc_bypass = 0; SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 212 52 -225 763 1594 -142 51 -216 696 1635 -116 49 -205 631 1670 47 -193 565 1701 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 213 34 -126 264 1787 1.2.11.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat 32 11 1.2.11.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat 32 11 547 1004 525 1003 503 1001 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 214 -4 -103 309 1187 -3 -102 281 1174 -1 -100 253 1159 227 1142 201 1124 177 1105 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 215 16 -141 314 1447 565 -161 17 -135 276 1436 609 -161 17 -129 239 1425 654 -161 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 216 26 -178 515 1555 238 -133 27 -172 465 1563 281 -142 27 -165 417 1568 324 -150 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 217 978 1371 -153 -149 909 1428 -145 -142 839 1482 -135 -135 771 1532 -122 -127 703 1579 -107 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 218 673, 242, 334, 740, 685, 255, 321, 733, 696, 268, 308, 726, 707, 281, 298, 726, 726, 298, High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 219 600, 118, 409, 853, 617, 128, 393, 847, 633, 139, 376, 841, 650, 149, 359, 835, 666, 160, SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 220 412, 588, 915, 431, 569, 918, 451, 549, 921, 470, 529, 922, 490, 47}; 1.2.11.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat 32 11 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 221 720 1001 695 1014 670 1025 644 1035 618 1044 592 1050 566 1056 540 1060 515 1062 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 222 913 1030 882 1057 849 1083 816 1107 783 1130 750 1150 715 1169 681 1185 646 1200 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 223 17 1224 0 1188 -15 1149 -28 1109 1027 -40 1064 1064 -50 1027 1109 984 1149 940 1188 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 224 672 -116 -46 1495 732 -121 -65 1455 793 -126 -81 1411 854 -130 -95 1364 915 -132 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 225 1371 -153 1428 -145 1482 -135 1532 -122 1579 -107 1622 1660 1693 1722 1747 1765 1778 1785 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 226 -18 -104 320 1869 91 -104 -16 -105 274 1887 121 -105 -13 -105 230 1897 153 -105 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 227: Video Compositer (Vcomp)
1-157, the Main and Aux layers are composited over the background color. Figure 1-157. Main and Auxiliary Layers Over Background MAIN BACKGROUND SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 228: Overlap Region
Figure 1-159. Cropping of Input Layers Main_H Aux_H Main_V_skip Aux_H_skip Main_H_skip Main_H_use Aux_H_use MAIN MAIN cropped cropped Background High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 229: Single Plane Output
Main_Y = VCOMP->reg7.cfg_dsply_main_y_origin Aux_X = VCOMP->reg8.cfg_dsply_aux_x_origin Aux_Y = VCOMP->reg8.cfg_dsply_aux_y_origin Background color configuration: = VCOMP->reg8.cfg_dsply_bckgrnd_y_val = VCOMP->reg8.cfg_dsply_bckgrnd_cb_val = VCOMP->reg8.cfg_dsply_bckgrnd_cr_val SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 230: Main Layer Only
Alternate fixed color can be selected for main and aux layers when needed as shown below. Main layer Fixed data enable/disable VCOMP→reg0.cfg_main_fixed_data_send High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 231: Conditions Where Valid Configurations May Not Work In A System
Figure 1-164. Conditions Where Valid Configurations May Not Work in a System MAIN BACKGROUND SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 232 + ----------------- + v + ------ + -------------- + v + ------------------- + --------------------------------- ------------------------------------ ------------------------------------ +-- High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 233: Video Port Direct Memory Access (Vpdma)
Data Transfer Descriptor that has a common format. The client that the channel is mapped to interprets the information in the descriptor to perform the requested data transfer. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 234 – Bitmap-2 Offset2 – Bitmap-2 Offset3 – Bitmap-1 Offset0 – Bitmap-1 Offset1 – Bitmap-1 Offset2 – Bitmap-1 Offset3 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 235: Memory Databus Write Order
SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 236: Inbound Data Transfer Descriptor Format
Channel field is free. If the Channel is not free when the list reaches a data transfer descriptor then the list will stall until the current transfer on the channel has completed. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 237: Data Packet Descriptor Word 0 Field Descriptions
The formats 14h, 15h, 16h, 17h, 27h, 37h are referred to as swap formats in this specification. Notify Send List Notification Interrupt upon last transfer of this channel Field Field Value SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 238 The Field bit is the field value of the data that will be passed down to the clients. If the data is interlaced, then this value should be cleared to 0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 239: Data Packet Descriptor Word 1 Field Description
The maximum supported transfer size is currently 2048. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 240: Data Packet Descriptor Word 2 Field Descriptions
Next Channel Next Channel to execute on a line or the channel to use in the generated write descriptor. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 241: Hdvpss Pressure And Priority Settings
Pressure[0] MReqPriority[2] MReqPriority[1] MReqPriority[0] (Mflag[1]) (Mflag[0]) Priority Bits Used in EMIF Arbitration Pressure Bits Used in Interconnect Arbitration SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 242: Priority Bit Fields
VPDMA to present a larger frame of data to the client while only fetching the required data. The currently supported maximum width is 4096. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 243: Data Packet Descriptor Word 4 Outbound Data Field Descriptions
1.2.13.3.1.5.2.4 Use Descriptor Register Bit 0 determines where the descriptor should be written. This bit MUST be set to 0. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 244: Data Packet Descriptor Word 5 Inbound Data Field Descriptions
. Tiled clients such as the noise filter should always set this to 0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 245: Configuration Descriptor Header Word0 Field Descriptions
This address should be on a 16 byte boundary so the lower 4 bits should always be 0. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 246: Configuration Descriptor Header Word3 Field Descriptions
A 1 indicates the payload is simply block data. The data is contiguous and starts at the offset of the destination as specified in word1. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 247: Destination Field Description
Reserved for future use Control The type of control descriptor that should be run by the List Manager SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 248: Control Descriptor Types Summary
LINE_COUNT where a pixel based event would occur. 15-0 LINE_COUNT Specify the line where a line based event would trigger High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 249: Sync On Client Field Descriptions (Word - 3)
Specifies the source used for the control event. 15-4 Reserved Reserved for future use Control Control type = 2h SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 250: Sync On Channel Field Descriptions (Word - 3)
0 then vpdma_descriptor_interrupt0 will fire. If source is 12 then vpdma_descriptor_interrupt12 will fire. Word 0, Word 1 and Word 2 are reserved. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 251: Send Interrupt Field Descriptions (Word - 3)
Description 31-27 Packet Type Host Packet Descriptor Type = Ch 26-4 Reserved Reserved Control Control type = 7h SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 252: Abort Channel Field Descriptions (Word - 3)
Host Packet Descriptor type = 0xC 26-4 Reserved This field controls the behavior of FID2 Control Control type = 9h High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 253 All types of RGB formats described in VPDMA section. VIN0 VIN1 VOUT1 VOUT0 Configuration inputs from Control Module SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 254: Vpdma Channels
(2) Table Load from Memory grpx2_clut Graphics 1 Color Lookup OTHER () grpx2_clut_clt (2) Table Load from Memory High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 255 Channel 9 0x37) vip1_mult_portb_src10 Video Input 1 Port B YUV (0x7, 0x17, 0x27, vip1_lo_uv (1) Channel 10 0x37) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 256 Ancillary Data Channel 5 vip1_mult_ancb_src6 Video Input 1 Port B OTHER (8) vip1_anc_b (2) Ancillary Data Channel 6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 257 Channel 10 0x37) vip2_mult_porta_src11 Video Input 2 Port A YUV (0x7, 0x17, 0x27, vip2_lo_y (21) Channel 11 0x37) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 258 Ancillary Data Channel 6 vip2_mult_anca_src7 Video Input 2 Port A OTHER (8) vip2_anc_a (21) Ancillary Data Channel 7 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 259 Video Input 2 Port B 420 YUV (0x1, 0x2, 0x7, vip2_lo_y (21) Data Luma 0x17, 0x27, 0x37) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 260 (18) Path 0 Chroma data type 0x7 is used half the data fetched will be thrown out.) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 261: Vpdma Client Buffering
11520 VP_WR vip1_porta_rgb vip1_up_uv vip1_porta_chroma 11520 VP_WR SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 262 4096 MEM_TO_MEM trans1_chroma transcode1_chroma 11520 TRANS_VID0 trans1_luma transcode1_luma 7680 TRANS_VID1 trans2_chroma transcode2_chroma 11520 TRANS_VID2 trans2_luma transcode2_luma 7680 TRANS_VID3 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 263 VP_WR2 vip2_mult_anca_src1 vip2_mult_anca_src2 vip2_mult_anca_src3 vip2_mult_anca_src4 vip2_mult_anca_src5 vip2_mult_anca_src6 vip2_mult_anca_src7 vip2_mult_anca_src8 vip2_mult_anca_src9 vip2_mult_anca_src10 vip2_mult_anca_src11 vip2_mult_anca_src12 vip2_mult_anca_src13 vip2_mult_anca_src14 vip2_mult_anca_src15 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 264: Hdvpss Client Functionality
1920 4096 Virtual Video Buffer, TILED trans2_chroma 1920 1920 Virtual Video Buffer with line buffer limitations, TILED High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 265: Hdvpss Interrupt From Vpdma
The data transfer in list 7 with the Notify Field set in the descriptor has completed vpdma_int_client Client Interrupt vpdma_int_descriptor Descriptor Interrupt SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 266: Hdvpss Interrupt Sources
High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 267 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 268 If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 269 If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 270 If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 271 If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 272 If a new channel has not been setup for the client then the client will be fully empty at this point. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 273 If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 274 If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 275 If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 276 If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 277 End of Frame signal to the receiving module. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 278 End of Frame signal to the receiving module. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 279 End of Frame signal from the transmitting module. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 280 A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 281 In this mode the data will always be sent out as 422 Interleaved data to the destination specified in the descriptor. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 282 The graphics ports in this device are tightly coupled with the VPDMA clients that service them. Each graphics port expects a list of data descriptors to describe each region that make up the frame. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 283: Graphics Region Descriptor Format
5 bits of TRANS_COLOR R/G/B color. trans color Word 7 Bits 31:8 Transparency Color (RGB24) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 284: Frame Configuration Descriptor Format
Coefficient for Horizontal TAP 0 Phase 6 coefh0_p7 Payload Word 7 Bits 25:16 Coefficient for Horizontal TAP 0 Phase 7 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 285 Coefficient for Vertical TAP 1 Phase 3 coefv1_p4 Payload Word 31 Bits 9:0 Coefficient for Vertical TAP 1 Phase 4 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 286 Payload Word 42 Bits 23:16 Average Filter accumulator averaging factor rav_rowacc Payload Word 43 Bits 7:0 Average Accumulator value weight High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 287: Example Graphics Output
Reg 1 Scaled Frame 2 Reg 2 Stenciled Reg 1 Scaled Stenciled Frame 3 Reg 2 Reg 3 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 288: Example Graphics List Description
The order to keep descriptors is as follows: 1. Configuration descriptors (To configure the Scaler in the path) 2. Outbound Descriptors 3. Inbound Descriptors High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 289: Y 4:4:4 (Data Type 0)
Y01 Y11 Y21 U01 U11 U21 V01 V11 V21 Y0M Y1M Y2M U0M U1M U2M V0M V1M V2M SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 290: Y 4:2:2 (Data Type 1)
Y00 Y10 Y20 Y00 Y10 Y20 Y01 Y11 Y21 Y01 Y11 Y21 Y0M Y1M Y2M Y0M Y1M Y2M High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 291: C 4:4:4 (Data Type 4)
U0M U1M U2M V01 V11 V21 V0M V1M V2M Y0M Y1M Y2M U0M U1M U2M V0M V1M V2M SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 292: C 4:2:2 (Data Type 5)
U01 V01 U11 V11 UN1 VN1 U0M V0M U1M V1M UNM VNM U0M V0M U1M V1M UNM VNM High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 293: Yc 4:2:2 (Data Type 7)
U00 V00 Y01 Y11 Y21 U0M Y1M V0M Y2M U1M Y3M V1M YNM VnM Y0M Y1M Y2M U00 V00 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 294: Yc 4:4:4 (Data Type 8)
U0M V0M Y1M U1M V1M Y01 Y11 Y21 U01 U11 U21 V01 V11 U0M U1M U2M V0M V1M High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 295: Cy 4:2:2 (Data Type 23H)
Figure 1-179. CY 4:2:2 (Data Type 23h) Memory Luma Chroma Client Y00 Y10 Y20 U00 V00 Y01 Y11 Y21 Y0M Y1M Y2M U00 V00 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 296: Cb 4:4:4 (Data Type 14H)
Y01 Y11 Y21 U0M V0M U1M V1M UNM VNM U0M V0M U1M V1M UNM VNM Y0M Y1M Y2M U0M V0M High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 297: Cb 4:2:0 (Data Type 16H)
Figure 1-183. CbY 4:2:2 (Data Type 17h) Memory Luma Chroma Client Y00 Y10 Y20 U00 V00 Y01 Y11 Y21 Y0M Y1M Y2M U0M V0M SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 298: Yc 4:2:2 (Data Type 27H)
U00 V00 Y01 Y11 Y21 U0M Y1M V0M Y2M U1M Y3M V1M YNM VnM Y0M Y1M Y2M U0M V0M High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 299: Rgb16-565 (Data Type 0)
5 bits for blue data, the middle 6 bits for green data and the upper 5 bits for red data. Figure 1-186. RGB16-565 (Data Type 0) Pixel in Memory Pixel to Client BG_RGB Register SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 300: Argb-1555 (Data Type 1)
4 bits for the blend value. Figure 1-188. ARGB-4444 (Data Type 2) Pixel in Memory Pixel to Client BG_RGB Register High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 301: Rgba-5551 (Data Type 3)
4 bits for red data. Figure 1-190. RGBA-4444 (Data Type 4) Pixel in Memory Pixel to Client BG_RGB Register SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 302: Argb24-6666 (Data Type 5)
BG_RGB Blend value for the Blend value. Figure 1-192. RGB24-888 (Data Type 6) Pixel in Memory Pixel to Client BG_RGB Register High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 303: Argb32-8888 (Data Type 7)
Figure 1-193. ARGB32-8888 (Data Type 7) Pixel in Memory Pixel to Client BG_RGB Register SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 304: Rgba24-6666 (Data Type 8)
6 bits for red data. Figure 1-194. RGBA24-6666 (Data Type 8) Pixel in Memory Pixel to Client BG_RGB Register High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 305: Rgba32-8888 (Data Type 9)
8 bits for red data. Figure 1-195. RGBA32-8888 (Data Type 9) Pixel in Memory Pixel to Client BG_RGB Register SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 306: Bitmap-8 (Data Type 20H)
256 by 32 CLUT Each Word is RGBA 32 Address to 0 0 0 0 CLUT Pixel to Client High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 307: Bitmap-4 Upper (Data Type 23H)
256 by 32 CLUT Each Word is RGBA 32 Address to 0 0 0 0 0 0 CLUT Pixel to Client SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 308: Bitmap-2 Offset1 (Data Type 25H)
256 by 32 CLUT Each Word is RGBA 32 Address to 1 0 0 0 0 0 CLUT Pixel to Client High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 309: Bitmap-2 Offset3 (Data Type 27H)
Each Word is RGBA 32 Address to 0 0 0 0 0 0 0 CLUT Pixel to Client SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 310: Bitmap-1 Offset1 (Data Type 29H)
Each Word is RGBA 32 Address to 0 2 0 0 0 0 0 CLUT Pixel to Client High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 311: Bitmap-1 Offset3 (Data Type 2Bh)
Each Word is RGBA 32 Address to 1 0 0 0 0 0 0 CLUT Pixel to Client SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 312: Bitmap-1 Offset5 (Data Type 2Dh)
Each Word is RGBA 32 Address to 1 1 0 0 0 0 0 CLUT Pixel to Client High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 313: Bitmap-1 Offset7 (Data Type 2Fh)
The Free channel data type is always ignored as it uses the same data type of the descriptor that first calls the free channel. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 314: Registers
CHR_DS module does not contain any MMRs. The CHR_DS module is enabled by selecting 420 data formatted output in the clkc_vip registers. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 315: Hdvpss Registers
5800h VIP_PARSER1 5A00h CSC_VIP1 5C00h SC_4 5D00h SD_VENC 5E00h HD_VENC_D_DVO1 6000h HD_VENC_A_HDCOMP 8000h HD_VENC_D_DVO2 A000h C200h VPDMA D000h SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 316: Chr_Us Registers
Upsampling Coeffs Section 1.3.1.5 CHR_US_reg5 Upsampling Coeffs Section 1.3.1.6 CHR_US_reg6 Upsampling Coeffs Section 1.3.1.7 CHR_US_reg7 Upsampling Coeffs Section 1.3.1.8 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 317: Chr_Us_Reg0 Register
01 = Mode B 15-2 ANCHOR_FID0_C1 C1 coefficient for Anchor Pixel. Used when field_id = 0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 318: Chr_Us_Reg1 Register
C2 coefficient for Anchor Pixel. Used when field_id = 0 17-16 Reserved Reserved 15-2 ANCHOR_FID0_C3 C3 coefficient for Anchor Pixel. Used when field_id = 0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 319: Chr_Us_Reg2 Register
C0 coefficient for Interpolated Pixel. Used when field_id = 0 17-16 Reserved Reserved 15-2 INTERP_FID0_C1 C1 coefficient for Interpolated Pixel. Used when field_id = 0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 320: Chr_Us_Reg3 Register
C2 coefficient for Interpolated Pixel. Used when field_id = 0 17-16 Reserved Reserved 15-2 INTERP_FID0_C3 C3 coefficient for Interpolated Pixel. Used when field_id = 0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 321: Chr_Us_Reg4 Register
C0 coefficient for Anchor Pixel. Used when field_id = 1 17-16 Reserved Reserved 15-2 ANCHOR_FID1_C1 C1 coefficient for Anchor Pixel. Used when field_id = 1 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 322: Chr_Us_Reg5 Register
C2 coefficient for Anchor Pixel. Used when field_id = 1 17-16 Reserved Reserved 15-2 ANCHOR_FID1_C3 C3 coefficient for Anchor Pixel. Used when field_id = 1 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 323: Chr_Us_Reg6 Register
C0 coefficient for Interpolated Pixel. Used when field_id = 1 17-16 Reserved Reserved 15-2 INTERP_FID1_C1 C1 coefficient for Interpolated Pixel. Used when field_id = 1 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 324: Chr_Us_Reg7 Register
C2 coefficient for Interpolated Pixel. Used when field_id = 1 17-16 Reserved Reserved 15-2 INTERP_FID1_C3 C3 coefficient for Interpolated Pixel. Used when field_id = 1 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 325: Cig Registers
CIG PIP Size Config Reg Section 1.3.2.9 CIG_reg9 CIG PIP Transparency Config Reg Section 1.3.2.10 CIG_reg10 CIG PIP Transparent Color Section 1.3.2.11 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 326: Cig_Reg0 Register
Enable Output Interlacing for Non-constrained output 0: Disabled 1: Enabled CIG_EN CIG module enable 0: Disabled (Bypass Mode) 1: CIG filter Enabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 327: Cig_Reg1 Register
DISP_W Output display Width (max = 1920) 15-11 Reserved Reserved 10-0 DISP_H Output display Height (max = 0x7FF) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 328: Cig_Reg2 Register
2: Mask 2 LSB bits 3: Mask 3 LSB bits TR_ENABLE Transparency Enable 0: Disable Transparency 1: Enable Transparency High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 329: Cig_Reg3 Register
Transparency Color 23:16 R 15:8 G 7:0 B (If the video pixel matches this color while transparency is enabled, the alpha value is forced to SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 330: Cig_Reg4 Register
2: Mask 2 LSB bits 3: Mask 3 LSB bits TR_ENABLE Transparency Enable 0: Disable Transparency 1: Enable Transparency High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 331: Cig_Reg5 Register
Transparency Color 23:16 R 15:8 G 7:0 B (If the video pixel matches this color while transparency is enabled, the alpha value is forced to SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 332: Cig_Reg6 Register
PIP Output display Width (max = 1920) 15-11 Reserved Reserved 10-0 PIP_DISP_H PIP Output display Height (max = 0x7FF) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 333: Cig_Reg7 Register
31-27 Reserved Reserved 26-16 PIP_X PIP window X position 15-11 Reserved Reserved 10-0 PIP_Y PIP window Y position SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 334: Cig_Reg8 Register
Reserved 10-0 PIP_H PIP window Height ( pip_y + pip_h must be less than or equal to disp_h) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 335: Cig_Reg9 Register
2: Mask 2 LSB bits 3: Mask 3 LSB bits TR_ENABLE Transparency Enable 0: Disable Transparency 1: Enable Transparency SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 336: Cig_Reg10 Register
Transparency Color 23:16 R 15:8 G 7:0 B (If the video pixel matches this color while transparency is enabled, the alpha value is forced to High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 337: Comp Registers
COMP HDCOMP Settings Section 1.3.3.4 COMP_sd_settings COMP SD Settings Section 1.3.3.5 COMP_back_color_settings COMP Background Color Settings Section 1.3.3.6 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 338: Comp_Status Register
HDMI/DVO1 Scan Format 1: interlace format 0: progressive format HDMI_ENABLE HDMI/DVO1 Blender enable 0 : Disabled 1 : Enabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 339: Comp_Hdmi_Settings Register
GRPX1 channel enable 0 : Disabled 1 : Enabled GRPX2_EN GRPX2 channel enable 0 : Disabled 1 : Enabled SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 340: Comp_Dvo2_Settings Register
GRPX1 channel enable 0 : Disabled 1 : Enabled GRPX2_EN GRPX2 channel enable 0 : Disabled 1 : Enabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 341: Comp_Hdcomp_Settings Register
GRPX1 channel enable 0 : Disabled 1 : Enabled GRPX2_EN GRPX2 channel enable 0 : Disabled 1 : Enabled SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 342: Comp_Sd_Settings Register
GRPX1 channel enable 0 : Disabled 1 : Enabled GRPX2_EN GRPX2 channel enable 0 : Disabled 1 : Enabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 343: Comp_Back_Color_Settings Register
0. It is also output to VENCs to be used if channel is not enabled or an underflow occurs SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 344: Csc Registers
Color Space Converter Reg03 Section 1.3.4.4 CSC_csc04 Color Space Converter Reg04 Section 1.3.4.5 CSC_csc05 Color Space Converter Reg05 Section 1.3.4.6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 345: Csc_Csc00 Register
1.893, 0x186E needs to be written in the register. (round)(-1.893*1024)= -1938 = 0x186E (2'S compliment format of - 1938 in 13-bit width) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 346: Csc_Csc01 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in CSC_csc00) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 347: Csc_Csc02 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in CSC_csc00) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 348: Csc_Csc03 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in CSC_csc00) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 349: Csc_Csc04 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in CSC_csc00) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 350: Csc_Csc05 Register
-2048 to 2047. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0 in CSC_csc04) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 351: Dei Registers
FMD Status Register 0 Section 1.3.5.13 dei_reg13 FMD Status Register 1 Section 1.3.5.14 dei_reg14 FMD Status Register 2 Section 1.3.5.15 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 352: Dei_Reg0 Register
28-27 Reserved Reserved 26-16 HEIGHT 1E0h Frame height 15-11 Reserved Reserved 10-0 WIDTH 2D0h Frame Width High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 353: Dei_Reg1 Register
Enable 1: Bypass MDT_TEMPMAX_BYPAS Spatio-temporal Maximum Filtering Bypass for motion valued used in EDI 0: Enable 1: Bypass SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 354: Dei_Reg2 Register
Note: 0 <= mdt_sf_sc_thr1 <= mdt_sf_sc_thr2 <= mdt_sf_sc_thr3 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 355: Dei_Reg3 Register
11: edge-directed interpolation for both luma and chroma Note that mode 00 and 01 are used for debug purpose SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 356: Dei_Reg4 Register
12-8 EDI_LUT1 EDI Lookup Table 1 Reserved Reserved EDI_LUT0 EDI Lookup Table 0 Note: 0<=EDI_LUT0 <=EDI_LUT1 <=EDI_LUT2 <=EDI_LUT3..<=EDI_LUT15 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 357: Dei_Reg5 Register
EDI Lookup Table 6 15-13 Reserved Reserved 12-8 EDI_LUT5 EDI Lookup Table 5 Reserved Reserved EDI_LUT4 EDI Lookup Table 4 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 358: Dei_Reg6 Register
EDI Lookup Table 10 15-13 Reserved Reserved 12-8 EDI_LUT9 EDI Lookup Table 9 Reserved Reserved EDI_LUT8 EDI Lookup Table 8 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 359: Dei_Reg7 Register
EDI Lookup Table 14 15-13 Reserved Reserved 12-8 EDI_LUT13 EDI Lookup Table 13 Reserved Reserved EDI_LUT12 EDI Lookup Table 12 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 360: Dei_Reg8 Register
Right boundary of FMD operation window Must be less than width 15-11 Reserved Reserved 10-0 FMD_WINDOW_MINX Left boundary of FMD operation window High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 361: Dei_Reg9 Register
Bottom boundary of FMD operation window Must be less than height/2 15-11 Reserved Reserved 10-0 FMD_WINDOW_MINY Top boundary of FMD operation window SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 362: Dei_Reg10 Register
0: Standard Deinterlacer Processing 1: Film Mode Deinterlacer Processing FMD_ENABLE Enable film mode processing 0: Disable 1: Enable High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 363: Dei_Reg11 Register
If the user prefers to be more conservative in using film mode, decrease this threshold. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 364: Dei_Reg12 Register
(fmd_bed_enable = 1) and the design is currently locked into film mode. 23-21 Reserved Reserved 20-0 FMD_CAF Detected combing artifacts High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 365: Dei_Reg13 Register
Description 31-28 Reserved Reserved 27-0 FMD_FIELD_DIFF Field difference (difference between two neighboring fields, one top and one bottom) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 366: Dei_Reg14 Register
Type Reset Description 31-20 Reserved Reserved 19-0 FMD_FRAME_DIFF Frame difference (difference between two top or two bottom fields) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 367: Grpx Registers
The graphics module (GRPX) is configured using VPDMA frame and region descriptors. Please refer to Section 1.2.5 Section 1.2.13.5.1.5 for instructions on how to configure the graphics module. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 368: Intc_Clkc_Control Registers
VENC Clock Select Register Section 1.3.7.41 118h clkc_venc_ena VENC Enable Register Section 1.3.7.42 11Ch clkc_range_map VC1 Range Map Register Section 1.3.7.43 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 369 Table 1-167. INTC_CLKC_CONTROL REGISTERS (continued) Offset Acronym Register Name Section 120h clkc_underflow VENC Underflow Status Register Section 1.3.7.44 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 370: Pid Register
RTL Release Version The PDR release number of this IP 10-8 MAJOR Major Release Number CUSTOM Custom IP MINOR Minor Release Number High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 371: Sysconfig Register
Type Reset Description 31-6 Reserved STANDBYMODE Standymode setting for PWRSTNDBY IPGeneric IDLEMODE Idlemode setting for PWRIDLE IPGenerc Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 372: Intc_Intr0_Status_Raw0 Register
VPDMA INT0 List7 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 373 VPDMA INT0 List0 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 374: Intc_Intr0_Status_Raw1 Register
VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 375 VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = _GROUP0_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 376: Intc_Intr0_Status_Ena0 Register
VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 377 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 378: Intc_Intr0_Status_Ena1 Register
DEI Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 379 _GROUP0_ENA status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 380: Intc_Intr0_Ena_Set0 Register
DEI Film Mode Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 381 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 382: Intc_Intr0_Ena_Set1 Register
VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = NA_SET disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 383 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 384: Intc_Intr0_Ena_Clr0 Register
DEI Film Mode Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 385 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 386: Intc_Intr0_Ena_Clr1 Register
DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 387 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 388: Intc_Intr1_Status_Raw0 Register
VPDMA INT0 List7 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 389 VPDMA INT0 List0 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 390: Intc_Intr1_Status_Raw1 Register
VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 391 VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = _GROUP0_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 392: Intc_Intr1_Status_Ena0 Register
VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 393 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 394: Intc_Intr1_Status_Ena1 Register
DEI Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 395 _GROUP0_ENA status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 396: Intc_Intr1_Ena_Set0 Register
DEI Film Mode Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 397 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 398: Intc_Intr1_Ena_Set1 Register
VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = NA_SET disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 399 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 400: Intc_Intr1_Ena_Clr0 Register
DEI Film Mode Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 401 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 402: Intc_Intr1_Ena_Clr1 Register
DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 403 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 404: Intc_Intr2_Status_Raw0 Register
VPDMA INT0 List7 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 405 VPDMA INT0 List0 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 406: Intc_Intr2_Status_Raw1 Register
VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 407 VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = _GROUP0_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 408: Intc_Intr2_Status_Ena0 Register
VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 409 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 410: Intc_Intr2_Status_Ena1 Register
DEI Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 411 _GROUP0_ENA status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 412: Intc_Intr2_Ena_Set0 Register
DEI Film Mode Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 413 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 414: Intc_Intr2_Ena_Set1 Register
VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = NA_SET disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 415 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 416: Intc_Intr2_Ena_Clr0 Register
DEI Film Mode Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 417 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 418: Intc_Intr2_Ena_Clr1 Register
DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 419 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 420: Intc_Intr3_Status_Raw0 Register
VPDMA INT0 List7 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 421 VPDMA INT0 List0 Complete Status Read indicates raw status 0 = MPLETE_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 422: Intc_Intr3_Status_Raw1 Register
VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 423 VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = _GROUP0_RAW inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 424: Intc_Intr3_Status_Ena0 Register
VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 425 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 426: Intc_Intr3_Status_Ena1 Register
DEI Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 427 _GROUP0_ENA status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 428: Intc_Intr3_Ena_Set0 Register
DEI Film Mode Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 429 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 430: Intc_Intr3_Ena_Set1 Register
VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = NA_SET disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 431 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 432: Intc_Intr3_Ena_Clr0 Register
DEI Film Mode Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 433 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 434: Intc_Intr3_Ena_Clr1 Register
DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 435 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 436: Intc_Eoi Register
Write to intr1 IP Generic Write 0x2 : Write to intr2 IP Generic Write 0x3 : Write to intr3 IP Generic Any other write value is ignored. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 437: Clkc_Clken Register
Graphics 1 Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled AUX_DP_EN Auxiliary Video Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 438 Primary Video Data Path Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled VPDMA_EN VPDMA Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 439: Clkc_Rst Register
DVO2 Video Encoder Reset 1 = Reset Enable 0 = Reset Disable HDCOMP_RST HDCOMP (HD_VENC_A) Video Encoder Reset 1 = Reset Enable 0 = Reset Disable SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 440 Primary Video Data Path Reset 1 = Reset Enable 0 = Reset Disable VPDMA_RST VPDMA Reset 1 = Reset Enable 0 = Reset Disable High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 441: Clkc_Dps Register
0 : DEI Path selected for VIP2 Scaler Output 1 : Independent Transcode Path1 selected for VIP1 Scaler Output SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 442 01 : Auxiliary (PIP) Path Input (from SC_M) 10 : Auxiliary (PIP) Memory Input (from VPDMA) 11 : Primary (HQ) Memory Input (from VPDMA) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 443: Clkc_Vip1Dps Register
Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 444 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 445 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 446: Clkc_Vip2Dps Register
Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 447 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 448 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 449: Clkc_Venc_Clksel Register
Digital Video Output 1 output clock 0 : hd_venc_d_clk 1 : hd_venc_d_clk/2 HD_VENC_D_CLK1X_SE HD_VENC_D_DVO1 clk1x source clock 0 : hd_venc_d_clk/2 1 : LECT hd_venc_d_clk SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 450: Clkc_Venc_Ena Register
HDCOMP VENC Enable 0 : Disabled 1 : Enabled HD_VENC_D_ENABLE HDMI/Digital Video Output 1 VENC Enable 0 : Disabled 1 : Enabled High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 451: Clkc_Range_Map Register
Range Mapping ON for Primary input RANGE_MAPUV_PRIM Range Map UV for Primary input RANGE_MAPY_PRIM Range Map Y for Primary input SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 452: Clkc_Underflow Register
HDMI/DVO1 VENC Underflow status Read 1 : HDMI/DVO1 Underflow Read 0 : HDMI/DVO1 NOT Underflow Write 1 to clear High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 453: Vpdma Registers
VPDMA Interrupt 1 Channel 5 Status Register Section 1.3.8.43 VPDMA_int1_channel5_int_mask VPDMA Interrupt 1 Channel 5 Mask Register Section 1.3.8.44 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 454 VPDMA Interrupt 3 Client 1 Mask Register Section 1.3.8.90 178h VPDMA_int3_list0_int_stat VPDMA Interrupt 3 List 0 Status Register Section 1.3.8.91 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 455 3F0h VPDMA_vip2_anc_a_cstat VPDMA VIP2 Ancillary A cstat Section 1.3.8.135 3F4h VPDMA_vip2_anc_b_cstat VPDMA VIP2 Ancillary B cstat Section 1.3.8.136 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 456: Vpdma_Pid Register
After bootup this bit states how DMA transaction are setup by lists or through register access. 0: Lists 1: Register Access MINOR Minor Release Number High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 457: Vpdma_List_Addr Register
Location of a new list of descriptors. This register must be written with the VPDMA configuration location after reset. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 458: Vpdma_List_Attr Register
VPDMA. This size can not be 0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 459: Vpdma_List_Stat_Sync Register
Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 460 Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 461: Vpdma_Vpi_Ctl_Address Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-217. VPDMA_vpi_ctl_address Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 462: Vpdma_Vpi_Ctl_Data Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-218. VPDMA_vpi_ctl_data Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 463: Vpdma_Bg_Rgb Register
The blend value to give on an RGB data port for a blank pixel when using virtual video buffering SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 464: Vpdma_Bg_Yuv Register
The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 465: Vpdma_Descriptor_Top Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-221. VPDMA_descriptor_top Register Field Descriptions Field Type Reset Description 31-0 Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 466: Vpdma_Descriptor_Bottom Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-222. VPDMA_descriptor_bottom Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 467: Vpdma_Current_Descriptor Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-223. VPDMA_current_descriptor Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 468: Vpdma_Descriptor_Status_Control Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-224. VPDMA_descriptor_status_control Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 469: Vpdma_Int0_Channel0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 470 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 471 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 472: Vpdma_Int0_Channel0_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 473 The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 474: Vpdma_Int0_Channel1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 475 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 476 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 477 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 478: Vpdma_Int0_Channel1_Int_Mask Register
PORTA_SRC15 an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 479 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 480 The interrupt for Graphics 0 Stencil should generate an interrupt on NCIL interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 481: Vpdma_Int0_Channel2_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 482 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 483 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 484 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 485: Vpdma_Int0_Channel2_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 486 PORTB_SRC13 an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 487 PORTB_SRC10 an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 488: Vpdma_Int0_Channel3_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 489 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 490 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 491 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 492: Vpdma_Int0_Channel3_Int_Mask Register
The interrupt for Video Input 2 Port A Channel 9 should generate an PORTA_SRC9 interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 493 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 494 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 495: Vpdma_Int0_Channel4_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 496 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 497 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 498 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 499: Vpdma_Int0_Channel4_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 500 The interrupt for Video Input 2 Port B Channel 7 should generate an PORTB_SRC7 interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 501 The interrupt for Video Input 2 Port B Channel 4 should generate an PORTB_SRC4 interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 502: Vpdma_Int0_Channel5_Int_Stat Register
Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 503 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 504 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 505 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 506: Vpdma_Int0_Channel5_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 507 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 508 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 509: Vpdma_Int0_Channel6_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 510: Vpdma_Int0_Channel6_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 511: Vpdma_Int0_Client0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 512 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 513 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 514: Vpdma_Int0_Client0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 515 The interrupt for should generate an interrupt on interrupt HROMA vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 516: Vpdma_Int0_Client1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 517 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 518 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 519 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 520: Vpdma_Int0_Client1_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 521 The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 522 The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 523: Vpdma_Int0_List0_Int_Stat Register
Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 524 Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 525 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 526: Vpdma_Int0_List0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt ESCRIPTOR_INT6 vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 527 The interrupt for should generate an interrupt on interrupt LETE vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 528 The interrupt for should generate an interrupt on interrupt LETE vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 529: Vpdma_Int1_Channel0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 530 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 531 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 532: Vpdma_Int1_Channel0_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 533 The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 534: Vpdma_Int1_Channel1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 535 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 536 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 537 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 538: Vpdma_Int1_Channel1_Int_Mask Register
PORTA_SRC15 an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 539 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 540 The interrupt for Graphics 0 Stencil should generate an interrupt on NCIL interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 541: Vpdma_Int1_Channel2_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 542 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 543 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 544 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 545: Vpdma_Int1_Channel2_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 546 PORTB_SRC13 an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 547 PORTB_SRC10 an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 548: Vpdma_Int1_Channel3_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 549 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 550 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 551 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 552: Vpdma_Int1_Channel3_Int_Mask Register
The interrupt for Video Input 2 Port A Channel 9 should generate an PORTA_SRC9 interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 553 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 554 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 555: Vpdma_Int1_Channel4_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 556 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 557 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 558 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 559: Vpdma_Int1_Channel4_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 560 The interrupt for Video Input 2 Port B Channel 7 should generate an PORTB_SRC7 interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 561 The interrupt for Video Input 2 Port B Channel 4 should generate an PORTB_SRC4 interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 562: Vpdma_Int1_Channel5_Int_Stat Register
Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 563 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 564 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 565 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 566: Vpdma_Int1_Channel5_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 567 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 568 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 569: Vpdma_Int1_Channel6_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 570: Vpdma_Int1_Channel6_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 571: Vpdma_Int1_Client0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 572 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 573 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 574: Vpdma_Int1_Client0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 575 The interrupt for should generate an interrupt on interrupt HROMA vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 576: Vpdma_Int1_Client1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 577 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 578 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 579 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 580: Vpdma_Int1_Client1_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 581 The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 582 The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 583: Vpdma_Int1_List0_Int_Stat Register
Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 584 Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 585 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 586: Vpdma_Int1_List0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt ESCRIPTOR_INT6 vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 587 The interrupt for should generate an interrupt on interrupt LETE vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 588 The interrupt for should generate an interrupt on interrupt LETE vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 589: Vpdma_Int2_Channel0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 590 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 591 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 592: Vpdma_Int2_Channel0_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 593 The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 594: Vpdma_Int2_Channel1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 595 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 596 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 597 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 598: Vpdma_Int2_Channel1_Int_Mask Register
PORTA_SRC15 an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 599 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 600 The interrupt for Graphics 0 Stencil should generate an interrupt on NCIL interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 601: Vpdma_Int2_Channel2_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 602 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 603 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 604 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 605: Vpdma_Int2_Channel2_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 606 PORTB_SRC13 an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 607 PORTB_SRC10 an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 608: Vpdma_Int2_Channel3_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 609 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 610 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 611 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 612: Vpdma_Int2_Channel3_Int_Mask Register
The interrupt for Video Input 2 Port A Channel 9 should generate an PORTA_SRC9 interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 613 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 614 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 615: Vpdma_Int2_Channel4_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 616 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 617 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 618 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 619: Vpdma_Int2_Channel4_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 620 The interrupt for Video Input 2 Port B Channel 7 should generate an PORTB_SRC7 interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 621 The interrupt for Video Input 2 Port B Channel 4 should generate an PORTB_SRC4 interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 622: Vpdma_Int2_Channel5_Int_Stat Register
Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 623 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 624 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 625 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 626: Vpdma_Int2_Channel5_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 627 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 628 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 629: Vpdma_Int2_Channel6_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 630: Vpdma_Int2_Channel6_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 631: Vpdma_Int2_Client0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 632 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 633 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 634: Vpdma_Int2_Client0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 635 The interrupt for should generate an interrupt on interrupt HROMA vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 636: Vpdma_Int2_Client1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 637 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 638 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 639 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 640: Vpdma_Int2_Client1_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 641 The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 642 The interrupt for should generate an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 643: Vpdma_Int2_List0_Int_Stat Register
Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 644 Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 645 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 646: Vpdma_Int2_List0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt ESCRIPTOR_INT6 vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 647 The interrupt for should generate an interrupt on interrupt LETE vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 648 The interrupt for should generate an interrupt on interrupt LETE vpdma_int2. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 649: Vpdma_Int3_Channel0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 650 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 651 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 652: Vpdma_Int3_Channel0_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 653 The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 654: Vpdma_Int3_Channel1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 655 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 656 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 657 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 658: Vpdma_Int3_Channel1_Int_Mask Register
PORTA_SRC15 an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 659 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 660 The interrupt for Graphics 0 Stencil should generate an interrupt on NCIL interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 661: Vpdma_Int3_Channel2_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 662 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 663 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 664 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 665: Vpdma_Int3_Channel2_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 666 PORTB_SRC13 an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 667 PORTB_SRC10 an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 668: Vpdma_Int3_Channel3_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 669 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 670 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 671 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 672: Vpdma_Int3_Channel3_Int_Mask Register
The interrupt for Video Input 2 Port A Channel 9 should generate an PORTA_SRC9 interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 673 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 674 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 675: Vpdma_Int3_Channel4_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 676 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 677 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 678 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 679: Vpdma_Int3_Channel4_Int_Mask Register
Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 680 The interrupt for Video Input 2 Port B Channel 7 should generate an PORTB_SRC7 interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 681 The interrupt for Video Input 2 Port B Channel 4 should generate an PORTB_SRC4 interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 682: Vpdma_Int3_Channel5_Int_Stat Register
Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 683 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 684 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 685 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 686: Vpdma_Int3_Channel5_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 687 Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 688 Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 689: Vpdma_Int3_Channel6_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 690: Vpdma_Int3_Channel6_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 691: Vpdma_Int3_Client0_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 692 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 693 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 694: Vpdma_Int3_Client0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. 11-6 Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 695 The interrupt for should generate an interrupt on interrupt HROMA vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 696: Vpdma_Int3_Client1_Int_Stat Register
This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 697 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 698 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 699 This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 700: Vpdma_Int3_Client1_Int_Mask Register
The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 701 The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 702 The interrupt for should generate an interrupt on interrupt vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 703: Vpdma_Int3_List0_Int_Stat Register
Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 704 Write a 1 to this field to clear the value. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 705 Write a 1 to this field to clear the value. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 706: Vpdma_Int3_List0_Int_Mask Register
The interrupt for should generate an interrupt on interrupt ESCRIPTOR_INT6 vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 707 The interrupt for should generate an interrupt on interrupt LETE vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 708 The interrupt for should generate an interrupt on interrupt LETE vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt signal. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 709: Vpdma_Dei_Hq_1_Chroma_Cstat Register
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 710: Vpdma_Dei_Hq_1_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 711: Vpdma_Dei_Hq_2_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 712: Vpdma_Dei_Hq_2_Chroma_Cstat Register
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 713: Vpdma_Dei_Hq_3_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 714: Vpdma_Dei_Hq_3_Chroma_Cstat Register
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 715: Vpdma_Dei_Hq_Mv_In_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 716: Vpdma_Dei_Hq_Mv_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 717: Vpdma_Dei_Sc_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 718: Vpdma_Pip_Wrbk_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 719: Vpdma_Sc_In_Chroma_Cstat Register
3 = each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 720: Vpdma_Sc_In_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 721: Vpdma_Sc_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 722: Vpdma_Comp_Wrbk_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 723: Vpdma_Grpx1_Data_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 724: Vpdma_Grpx2_Data_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 725: Vpdma_Grpx3_Data_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 726: Vpdma_Vip1_Lo_Y_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 727: Vpdma_Vip1_Lo_Uv_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 728: Vpdma_Vip1_Up_Y_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 729: Vpdma_Vip1_Up_Uv_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 730: Vpdma_Vip2_Lo_Y_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 731: Vpdma_Vip2_Lo_Uv_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 732: Vpdma_Vip2_Up_Y_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 733: Vpdma_Vip2_Up_Uv_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 734: Vpdma_Grpx1_St_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 735: Vpdma_Grpx2_St_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 736: Vpdma_Grpx3_St_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 737: Vpdma_Nf_422_In_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 738: Vpdma_Nf_420_Y_In_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 739: Vpdma_Nf_420_Uv_In_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 740: Vpdma_Nf_420_Y_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 741: Vpdma_Nf_420_Uv_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 742: Vpdma_Vbi_Sdvenc_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 743: Vpdma_Vpi_Ctl_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 744: Vpdma_Hdmi_Wrbk_Out_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 745: Vpdma_Trans1_Chroma_Cstat Register
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 746: Vpdma_Trans1_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 747: Vpdma_Trans2_Chroma_Cstat Register
3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines. Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 748: Vpdma_Trans2_Luma_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 749: Vpdma_Vip1_Anc_A_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 750: Vpdma_Vip1_Anc_B_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 751: Vpdma_Vip2_Anc_A_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 752: Vpdma_Vip2_Anc_B_Cstat Register
6 = Change in value of List Manager Internal Field - 2 7 = Start whenever channel is free Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 753: Hd_Venc_D Registers
Compositor IF Control Register Section 1.3.9.25 HD_VENC_D_cfg25 Compositor IF Control Register Section 1.3.9.26 1000h- HD_VENC_D_GAMMA_LUT Gamma Lookup Table Section 1.3.9.27 1FFFh SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 754: Hd_Venc_D_Cfg0 Register
1: Active Low I_DVO_V This bit controls the polarity of DVO_VS signal. 0: Active High 1: Active Low High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 755 0 : Color space conversion is engaged 1 : Bypass Reserved Reserved I_PN Scan format: 0 : Progressive 1 : Interlace Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 756: Hd_Venc_D_Cfg1 Register
1.893, 0x186E needs to be written in the register. (round)(-1.893*1024)= -1938 = 0x186E (2'S compliment format of - 1938 in 13-bit width) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 757: Hd_Venc_D_Cfg2 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 758: Hd_Venc_D_Cfg3 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 759: Hd_Venc_D_Cfg4 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 760: Hd_Venc_D_Cfg5 Register
-4 to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 761: Hd_Venc_D_Cfg6 Register
-2048 to 2047. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0 in HD_VENC_D_cfg5) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 762: Hd_Venc_D_Cfg7 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-357. HD_VENC_D_cfg7 Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 763: Hd_Venc_D_Cfg8 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-358. HD_VENC_D_cfg8 Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 764: Hd_Venc_D_Cfg9 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-359. HD_VENC_D_cfg9 Register Field Descriptions Field Type Reset Description 31-20 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 765: Hd_Venc_D_Cfg10 Register
Defines the total number of lines per frame. 11-0 PIXELS Defines the total number of pixels per line. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 766: Hd_Venc_D_Cfg11 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-361. HD_VENC_D_cfg11 Register Field Descriptions Field Type Reset Description 31-24 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 767: Hd_Venc_D_Cfg12 Register
31-24 Reserved Reserved 23-12 ACT_PIX Defines the number of active pixels in one video line. 11-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 768: Hd_Venc_D_Cfg13 Register
The high-4-bits of the delay counter of VENC_EN signal.. the low 8- bit of this counter is specified in CFG20 27-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 769: Hd_Venc_D_Cfg14 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-364. HD_VENC_D_cfg14 Register Field Descriptions Field Type Reset Description 31-24 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 770: Hd_Venc_D_Cfg15 Register
This parameter defines the SAV location in embedded sync mode and the location of the first active pixel on the DVO output in discrete sync mode. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 771: Hd_Venc_D_Cfg16 Register
11-0 DVO_HS_ST Defines the starting location of the DVO_HS pulse on each line. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 772: Hd_Venc_D_Cfg17 Register
Defines the first active line of second field in a frame. This parameter is only used in interlace mode. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 773: Hd_Venc_D_Cfg18 Register
Defines the number of active lines in the second field. This parameter is only used in interlace mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 774: Hd_Venc_D_Cfg19 Register
Defines the starting location of the DVO_VS of the second field. This parameter is only used in interlace mode. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 775: Hd_Venc_D_Cfg20 Register
Defines the starting location of the second field in interlace mode. This parameter is only used in interlace mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 776: Hd_Venc_D_Cfg21 Register
This parameters defines when the first pixel on each line must appear at the input of the HD_VENC (a fixed offset from DVO_AVST_H). OSD_AVST_H = DVO_AVST_H – 8. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 777: Hd_Venc_D_Cfg22 Register
(The line number starts at 0) 11-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 778: Hd_Venc_D_Cfg23 Register
Defines the first active line of second field in a frame. This parameter is only used in interlace mode. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 779: Hd_Venc_D_Cfg24 Register
Defines the number of active lines in the second field. This parameter is only used in interface mode. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 780: Hd_Venc_D_Cfg25 Register
DTV_FID to switch about 1/3 into the VBI period, giving sufficient timing margin for DMA set-up and video pipeline fill-up prior to the next active video period. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 781: Hd_Vend_D_Gamma_Lut Register
(controlled by HD_VENC_D_cfg0.BYPS_GC), this MMR area must be loaded by software before enabling HD_VENC_D. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 782: Noise_Filter Registers
NF Saved Noise Frame Y Data Reg Section 1.3.10.9 nf_reg9 NF Saved Noise Frame UV Data Reg Section 1.3.10.10 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 783: Nf_Reg0 Register
1x: DMA disabled.. Output Forced to Black (for first pass through the NF processing with no valid REF frame in the memory) NF_EN NF Enable: 0: Disabled 1: Enabled SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 784: Nf_Reg1 Register
31-27 Reserved 26-16 HEIGHT Number of lines per frame 15-11 Reserved 10-0 WIDTH Number of pixels per line High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 785: Nf_Reg2 Register
Spatial high-frequency filter strength of Y channel. 0 means disabled. _HIGH SPATIAL_STRENGTH_Y Spatial low-frequency filter strength of Y channel. 0 means disabled. _LOW SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 786: Nf_Reg3 Register
Spatial high-frequency filter strength of U channel. 0 means _HIGH disabled. SPATIAL_STRENGTH_U Spatial low-frequency filter strength of U channel. 0 means disabled. _LOW High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 787: Nf_Reg4 Register
The smallest noise level to fully trigger temporal filter. GGER_NOISE Reserved TEMPORAL_STRENGTH Temporal filter strength. 0 means disabled. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 788: Nf_Reg5 Register
Type Reset Description 31-9 Reserved MAX_NOISE Max of the possible noise level. NOISE_IIR_COEFFICIEN Noise level IIR filter coefficient. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 789: Nf_Reg6 Register
A tile is considered pure white if all pixel values are above pure_white_threshold. Reserved PURE_BLACK_THRESH A tile is considered pure black if all pixel values are below pure_black_threshold. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 790: Nf_Reg7 Register
Saved Frame Noise Register bank index (used to select one of 32 NDEX registers when accessing NF_REG8 or NF_REG9) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 791: Nf_Reg8 Register
Frame_noise_read_index register (Write) Value to be written to the Frame_noise_y selected by NF_REG0(nf_video_index) at the beginning of a new frame SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 792: Nf_Reg9 Register
Frame_noise_read_index register (Write) Value to be written to the Frame_noise_v selected by NF_REG0(nf_video_index) at the beginning of a new frame High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 793: Sc_M Registers
Section 1.3.11.20 SC_M_cfg_sc24 SC Trimmer Config Reg 0 Section 1.3.11.21 SC_M_cfg_sc25 SC Trimmer Config Reg 1 Section 1.3.11.22 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 794: Sc_M_Cfg_Sc0 Register
Typically, it is used when (horizontal scale ratio < 0.25). (3) This register is DON’T CARE when cfg_auto_hs = 1. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 795 This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 796: Sc_M_Cfg_Sc1 Register
In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 797: Sc_M_Cfg_Sc2 Register
In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 798: Sc_M_Cfg_Sc3 Register
In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 799: Sc_M_Cfg_Sc4 Register
This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 800: Sc_M_Cfg_Sc5 Register
For the interlace input.. it should be the number of lines per field. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 801: Sc_M_Cfg_Sc6 Register
(for progressive format or top field of interlace format) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 802: Sc_M_Cfg_Sc8 Register
The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 803: Sc_M_Cfg_Sc9 Register
((cfg_dcm_2x==0) && (cfg_dcm_4x==1) ) then lin_acc_inc = round(2^24*(srcWi/4) /(tarWi)) where srcWi and tarWi are the inner source width and the inner target width respectively. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 804: Sc_M_Cfg_Sc10 Register
It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in SC_CFG11 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 805: Sc_M_Cfg_Sc11 Register
Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 806: Sc_M_Cfg_Sc12 Register
In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 807: Sc_M_Cfg_Sc13 Register
This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 808: Sc_M_Cfg_Sc17 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-402. SC_M_cfg_sc17 Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 809: Sc_M_Cfg_Sc18 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-403. SC_M_cfg_sc18 Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 810: Sc_M_Cfg_Sc19 Register
This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 811: Sc_M_Cfg_Sc20 Register
This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 812: Sc_M_Cfg_Sc21 Register
CFG_NL_LO_THR This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 813: Sc_M_Cfg_Sc22 Register
CFG_NL_HI_THR This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 814: Sc_M_Cfg_Sc23 Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-408. SC_M_cfg_sc23 Register Field Descriptions Field Type Reset Description 31-0 Reserved Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 815: Sc_M_Cfg_Sc24 Register
15-11 Reserved 10-0 CFG_ORG_H This parameter is used by the trimmer. Height of the original input image. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 816: Sc_M_Cfg_Sc25 Register
CFG_OFF_H This parameter is used by the trimmer. Vertical offset from the top of the original input image. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 817: Sd_Venc Registers
Section 1.3.12.41 11Ch SD_VENC_upf0 2x Upsampling Coefficient 0 Section 1.3.12.42 120h SD_VENC_upf1 2x Upsampling Coefficient 1 Section 1.3.12.43 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 818 DAC 2x Upsampling Coefficient 1 Section 1.3.12.52 15Ch SD_VENC_dactst DAC Test Mode Section 1.3.12.53 1FCh SD_VENC_vtest Internal Test Register Section 1.3.12.54 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 819: Sd_Venc_Pid Register
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset Table 1-412. SD_VENC_pid Register Field Descriptions Field Type Reset Description 31-0 4FFF0000h Revision ID. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 820: Sd_Venc_Vmod Register
Video encoder enable. Setting 1 brings this module into operation. Setting 0 resets internal circuits in this module. 0: Video encoder reset 1: Video encoder enable High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 821: Sd_Venc_Slave Register
Master/slave select. Set 1 to operate this module in slave mode in synchronization with external sync signal. 0: Master mode 1: Slave mode SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 822: Sd_Venc_Size Register
Vertical interval. Specify the number of lines per frame. 15-13 Reserved 12-0 HITV 6B4h Horizontal interval. Specify the number of clocks per line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 823: Sd_Venc_Pol Register
DTV VSYNC output polarity. 0: Active H 1: Active L DTV_HS_POL DTV HSYNC output polarity 0: Active H 1: Active L SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 824: Sd_Venc_Dtvs0 Register
31-29 Reserved 28-16 DTV_HS_H_STP DTV HSYNC output stop pixel. 15-13 Reserved 12-0 DTV_HS_H_STA DTV HSYNC output start pixel. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 825: Sd_Venc_Dtvs1 Register
31-29 Reserved 28-16 DTV_VS_H_STP DTV VSYNC output stop pixel. 15-13 Reserved 12-0 DTV_VS_H_STA DTV VSYNC output start pixel. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 826: Sd_Venc_Dtvs2 Register
31-29 Reserved 28-16 DTV_VS_V_STP DTV VSYNC output stop line. 15-13 Reserved 12-0 DTV_VS_V_STA DTV VSYNC output start line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 827: Sd_Venc_Dtvs3 Register
Table 1-420. SD_VENC_dtvs3 Register Field Descriptions Field Type Reset Description 31-13 Reserved 12-0 DTV_FID_H_STA DTV FID output toggle pixel position. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 828: Sd_Venc_Dtvs4 Register
DTV FID output start field for fid=0. Optionally works as force FID toggle enable in progressive or non-interlace mode. 12-0 DTV_FID_V_STA0 DTV FID output start line for fid=0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 829: Sd_Venc_Dtvs5 Register
31-29 Reserved 28-16 DTV_AVID_H_STP DTV AVID output stop pixel. 15-13 Reserved 12-0 DTV_AVID_H_STA DTV AVID output start pixel. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 830: Sd_Venc_Dtvs6 Register
DTV AVID output stop line for fid=0. 15-13 Reserved 12-0 DTV_AVID_V_STA0 DTV AVID output start line for fid=0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 831: Sd_Venc_Dtvs7 Register
DTV AVID output stop line for fid=1. 15-13 Reserved 12-0 DTV_AVID_V_STA1 DTV AVID output start line for fid=1. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 832: Sd_Venc_Tvdetgp0 Register
Reset Description 31-29 Reserved 28-16 TVDETGP_H_STP TVDETGP output stop pixel. 15-13 Reserved 12-0 TVDETGP_H_STA TVDETGP output start pixel. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 833: Sd_Venc_Tvdetgp1 Register
Reset Description 31-29 Reserved 28-16 TVDETGP_V_STP TVDETGP output stop line. 15-13 Reserved 12-0 TVDETGP_V_STA TVDETGP output start line. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 834: Sd_Venc_Irq0 Register
Reset Description 31-29 Reserved 28-16 IRQ_V_STA IRQ output start line 15-13 Reserved 12-0 IRQ_H_STA IRQ output start pixel. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 835: Sd_Venc_Estat Register
L21DO. This bit is automatically cleared to 0 when a caption data transmission is completed on the line 21(NTSC) or 22(PAL) in odd field. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 836: Sd_Venc_Ectl Register
DAC 2x oversampling enable. 0: Off 1: On 2x up-sampling enable. 0: Off 1: On Gamma correction 0: Off 1: On High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 837: Sd_Venc_Etmg0 Register
Reserved 28-16 AV_H_STP 694h Active video horizontal stop position. 15-13 Reserved 12-0 AV_H_STA Active video horizontal start position. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 838: Sd_Venc_Etmg1 Register
Active video vertical stop position for fid=0. 15-13 Reserved 12-0 AV_V_STA0 Active video vertical start position for fid=0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 839: Sd_Venc_Etmg2 Register
Active video vertical stop position for fid=1. 15-13 Reserved 12-0 AV_V_STA1 Active video vertical start position for fid=1. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 840: Sd_Venc_Etmg3 Register
Type Reset Description 31-25 Reserved 24-16 BST_H_STP Color burst stop position. 15-9 Reserved BST_H_STA Color burst start position. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 841: Sd_Venc_Etmg4 Register
Reset Description 31-29 Reserved 28-16 VBI_H_STP VBI request stop position. 15-13 Reserved 12-0 VBI_H_STA VBI request start position. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 842: Sd_Venc_Cvbs0 Register
Type Reset Description 31-28 Reserved 27-16 CSLVL 344h CVBS sync amplitude. 15-12 Reserved 11-0 CTLVL CVBS sync-tip amplitude. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 843: Sd_Venc_Cvbs1 Register
YLPF CVBS luma LPF enable 0: Off 1: On CPSR CVBS picture sync ratio 0: 10:4 1: 7:3 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 844: Sd_Venc_Ccsc0 Register
Coefficients of color space converter for CVBS. s6.6 15-13 Reserved 12-0 CCSCA0 11Dh Coefficients of color space converter for CVBS. s6.6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 845: Sd_Venc_Ccsc1 Register
Coefficients of color space converter for CVBS. s8.4 15-13 Reserved 12-0 CCSCC0 Coefficients of color space converter for CVBS. s6.6 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 846: Sd_Venc_Ccsc2 Register
Table 1-439. SD_VENC_ccsc2 Register Field Descriptions Field Type Reset Description 31-13 Reserved 12-0 CCSCE0 Coefficients of color space converter for CVBS. s12.0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 847: Sd_Venc_Ccsc3 Register
Coefficients of color space converter for CVBS. s6.6 15-13 Reserved 12-0 CCSCA1 1F74h Coefficients of color space converter for CVBS. s6.6 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 848: Sd_Venc_Ccsc4 Register
Coefficients of color space converter for CVBS. s8.4 15-13 Reserved 12-0 CCSCC1 1FB9h Coefficients of color space converter for CVBS. s6.6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 849: Sd_Venc_Ccsc5 Register
Table 1-442. SD_VENC_ccsc5 Register Field Descriptions Field Type Reset Description 31-13 Reserved 12-0 CCSCE1 Coefficients of color space converter for CVBS. s12.0 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 850: Sd_Venc_Ccsc6 Register
Coefficients of color space converter for CVBS. s6.6 15-13 Reserved 12-0 CCSCA2 1F06h Coefficients of color space converter for CVBS. s6.6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 851: Sd_Venc_Ccsc7 Register
Coefficients of color space converter for CVBS. s8.4 15-13 Reserved 12-0 CCSCC2 12Ah Coefficients of color space converter for CVBS. s6.6 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 852: Sd_Venc_Ccsc8 Register
Table 1-445. SD_VENC_ccsc8 Register Field Descriptions Field Type Reset Description 31-13 Reserved 12-0 CCSCE2 Coefficients of color space converter for CVBS. s12.0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 853: Sd_Venc_Cygclp Register
Reserved 28-16 CYLCLP CVBS Y Lower Limit. s12.0 15-13 Reserved 12-0 CYUCLP FFFh CVBS Y Upper Limit. s12.0 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 854: Sd_Venc_Cubclp Register
28-16 CULCLP 1800h CVBS U Lower Limit. s12.0 15-13 Reserved 12-0 CUUCLP 7FFh CVBS U Upper Limit. s12.0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 855: Sd_Venc_Cvrclp Register
28-16 CVLCLP 1800h CVBS V Lower Limit. s12.0 15-13 Reserved 12-0 CVUCLP 7FFh CVBS V Vpper Limit. s12.0 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 856: Sd_Venc_Ylpf0 Register
Luma LPF coefficient 2. s0.7. 15-8 YLPFC1 Luma LPF coefficient 1. s0.7. YLPFC0 Luma LPF coefficient 0. s0.7. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 857: Sd_Venc_Ylpf1 Register
Type Reset Description 31-16 Reserved 15-8 YLPFC5 Luma LPF coefficient 5. s0.7. YLPFC4 Luma LPF coefficient 4. s0.7. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 858: Sd_Venc_Clpf0 Register
Chroma LPF coefficient 2. s0.7. 15-8 CLPFC1 Chroma LPF coefficient 1. s0.7. CLPFC0 Chroma LPF coefficient 0. s0.7. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 859: Sd_Venc_Clpf1 Register
Type Reset Description 31-16 Reserved 15-8 CLPFC5 Chroma LPF coefficient 5. s0.7. CLPFC4 Chroma LPF coefficient 4. s0.7. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 860: Sd_Venc_Upf0 Register
2x up-sampling filter coefficient 2. s0.7. 15-8 UPFC1 2x up-sampling filter coefficient 1. s0.7. UPFC0 2x up-sampling filter coefficient 0. s0.7. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 861: Sd_Venc_Upf1 Register
2x up-sampling filter coefficient 6. s0.7. 15-8 UPFC5 2x up-sampling filter coefficient 5. s0.7. UPFC4 2x up-sampling filter coefficient 4. s0.7. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 862: Sd_Venc_L21Ctl Register
21 for odd field and the line 284 for even field (line 22 and 335 for PAL). 0: No data output 1: Odd field 2: Even field 3: Both fields High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 863: Sd_Venc_L21Do Register
Closed caption data1 (odd field). Specify the ASCII code of the 2nd byte to be transmitted in closed captioning for odd field. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 864: Sd_Venc_L21De Register
Closed caption data1 (even field). Specify the ASCII code of the 2nd byte to be transmitted in closed captioning for even field. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 865: Sd_Venc_Wss Register
WSS data register (525i) bit1-0: WORD0 bit5-2: WORD1 bit13- 6:WORD2 bit19-14: CRC (625i) bit3-0: GROUP1 bit7-4: GROUP2 bit10-8: GROUP3 bit13-11: GROUP4 bit19-14: unused SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 866: Sd_Venc_Scctl0 Register
Sub-carrier frequency parameter 0. Default is 135. 15-10 Reserved SCSD Sub-carrier initial phase value. The degree can be specified by SCSD/1024*360. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 867: Sd_Venc_Scctl1 Register
Sub-carrier frequency parameter 2. Default is 33. Fsc = (SCP0 + SCP1/SCP2) * Fin / 1024 15-0 SCP1 Sub-carrier frequency parameter 1. Default is 25. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 868: Sd_Venc_Dacsel Register
DAC1 output select. See DAC0S. DA0S DAC0 output select. 0: CVBS 1: S-Video Y 2: S-Video; 3-15: Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 869: Sd_Venc_Dupf0 Register
DUPFC1 DAC 2x oversampling filter coefficient 1. s0.7. (Default=0) DUPFC0 DAC 2x oversampling filter coefficient 0. s0.7. (Default=0) SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 870: Sd_Venc_Dupf1 Register
DUPFC5 DAC 2x oversampling filter coefficient 5. s0.7. (Default=-20) DUPFC4 DAC 2x oversampling filter coefficient 4. s0.7. (Default=6) High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 871: Sd_Venc_Dactst Register
DALVL register to DAC and directly outputs from DAOUT. 0: Normal 1: DC output mode 15-12 Reserved 11-0 DALVL DAC DC level control SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 872: Sd_Venc_Vtest Register
Table 1-465. SD_VENC_vtest Register Field Descriptions Field Type Reset Description 31-0 VTST Reserved for internal testing. Should be always zero for normal usage. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 873: Vcomp Registers
VCOMP Display Register 5 Section 1.3.13.11 VCOMP_reg11 VCOMP Display Register 6 Section 1.3.13.12 VCOMP_reg12 VCOMP Display Register 7 Section 1.3.13.13 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 874: Vcomp_Reg0 Register
Number of lines in a field or frame from the incoming main source MLINES 15-12 Reserved Reserved 11-0 CFG_MAIN_NATIVE_NU Number of pixels per line from the incoming main source MPIX_PER_LINE High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 875: Vcomp_Reg1 Register
This field allows the input picture to be clipped. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 876: Vcomp_Reg2 Register
This field allows the input picture to be clipped. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 877: Vcomp_Reg3 Register
Number of lines in a field or frame from the incoming aux source LINES 15-12 Reserved Reserved 11-0 CFG_AUX_NATIVE_NUM Number of pixels per line from the incoming aux source PIX_PER_LINE SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 878: Vcomp_Reg4 Register
This field allows the input picture to be clipped. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 879: Vcomp_Reg5 Register
This field allows the input picture to be clipped. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 880: Vcomp_Reg6 Register
Number of lines in a field or frame for the output picture. 15-12 Reserved Reserved 11-0 CFG_DSPLY_NUMPIX_P Number of pixels per line for the output picture. ER_LINE High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 881: Vcomp_Reg7 Register
(x..y) = (0..0) is the top left corner of the display. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 882: Vcomp_Reg8 Register
(x..y) = (0..0) is the top left corner of the display. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 883: Vcomp_Reg9 Register
CFG_DSPLY_BCKGRND Background Cb/Chroma value for the display output. _CB_VAL CFG_DSPLY_BCKGRND Background Y/Luma value for the display output. _Y_VAL SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 884: Vcomp_Reg10 Register
Only the downstream output of pixel data is delayed. Generally.. this register should be set to 0x0. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 885: Vcomp_Reg11 Register
Used when main_fixed_data_send = 1. CFG_DSPLY_ALT_MAIN Alternate Main Y/Luma value for the background display output. _Y_VAL Used when main_fixed_data_send = 1. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 886: Vcomp_Reg12 Register
Used when aux_fixed_data_send = 1. CFG_DSPLY_ALT_AUX_ Alternate Aux Y/Luma value for the background display output. Used Y_VAL when aux_fixed_data_send = 1. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 887: Vip_Parser Registers
Width and Height for Source 15 Section 1.3.14.28 5_size VIP_PARSER_output_port_b_src0 Width and Height for Source 0 Section 1.3.14.29 _size SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 888 Cfg Disable Active Srcnum Vector Input for Port A Section 1.3.14.55 VIP_PARSER_xtra7_port_b Cfg Disable Active Srcnum Vector Input for Port B Section 1.3.14.56 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 889: Vip_Parser_Main Register
This prevents MPU or DSP to go through every byte to check if the data has to be clipped. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 890: Vip_Parser_Port_A Register
1 = Reset Port A logic. Must be set to '0' again by the software for the module to function. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 891: Vip_Parser_Port_A Register Field Descriptions
Typically, this will result in different configuration for fid_polarity between PAL and NTSC modes. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 892 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 893: Vip_Parser_Xtra_Port_A Register
Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 894: Vip_Parser_Port_B Register
1 = Reset Port B logic. Must be set to '0' again by the software for the module to function. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 895: Vip_Parser_Port_B Register Field Descriptions
Typically, this will result in different configuration for fid_polarity between PAL and NTSC modes. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 896 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 897: Vip_Parser_Xtra_Port_B Register
Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 898: Vip_Parser_Fiq_Mask Register
OUTPUT_FIFO_PRTB_Y Output FIFO Port B Luma Overflow Mask UV_OF OUTPUT_FIFO_PRTA_A Output FIFO Port A Ancillary Overflow Mask NC_OF High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 899 Port A Async FIFO Overflow FIQ Mask PRTB_VDET_MASK Port B Video Detect FIQ Mask PRTA_VDET_MASK Port A Video Detect FIQ Mask SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 900: Vip_Parser_Fiq_Clear Register
UV_CLR OUTPUT_FIFO_PRTA_A Write '1' followed by '0' to Clear Output FIFO Port A Ancillary NC_CLR Overflow FIQ Reserved High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 901 Write '1' followed by '0' to Clear Video Detect FIQ for Port B PRTA_VDET_CLR Write '1' followed by '0' to Clear Video Detect FIQ for Port A SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 902: Vip_Parser_Fiq_Status Register
OUTPUT_FIFO_PRTB_A Output FIFO Port B Ancillary Overflow Status NC_STATUS OUTPUT_FIFO_PRTB_C Output FIFO Port B Chroma Overflow Status HROMA_STATUS High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 903 Async FIFO Port A Overflow Status ATUS PRTB_VDET_STATUS VDET Status for Port B PRTA_VDET_STATUS VDET Status for Port A SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 904: Vip_Parser_Output_Port_A_Src_Fid Register
For Source ID 9 from Port A.. Source Field ID for Previous Field URCE_FID PRTA_SRC8_CURR_SO For Source ID 8 from Port A.. Source Field ID for Current Field URCE_FID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 905: Vip_Parser_Output_Port_A_Src_Fid Register Field Descriptions
For Source ID 0 from Port A.. Source Field ID for Current Field URCE_FID PRTA_SRC0_PREV_SO For Source ID 0 from Port A.. Source Field ID for Previous Field URCE_FID SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 906: Vip_Parser_Output_Port_A_Enc_Fid Register
For Source ID 9 from Port A.. Encoder Field ID for Previous Field _FID PRTA_SRC8_CURR_EN For Source ID 8 from Port A.. Encoder Field ID for Current Field C_FID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 907: Vip_Parser_Output_Port_A_Enc_Fid Register Field Descriptions
For Source ID 0 from Port A.. Encoder Field ID for Current Field C_FID PRTA_SRC0_PREV_ENC For Source ID 0 from Port A.. Encoder Field ID for Previous Field _FID SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 908: Vip_Parser_Output_Port_B_Src_Fid Register
For Source ID 9 from Port B.. Source Field ID for Previous Field URCE_FID PRTB_SRC8_CURR_SO For Source ID 8 from Port B.. Source Field ID for Current Field URCE_FID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 909: Vip_Parser_Output_Port_B_Src_Fid Register Field Descriptions
For Source ID 0 from Port B.. Source Field ID for Current Field URCE_FID PRTB_SRC0_PREV_SO For Source ID 0 from Port B.. Source Field ID for Previous Field URCE_FID SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 910: Vip_Parser_Output_Port_B_Enc_Fid Register
For Source ID 9 from Port B.. Encoder Field ID for Previous Field _FID PRTB_SRC8_CURR_EN For Source ID 8 from Port B.. Encoder Field ID for Current Field C_FID High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 911: Vip_Parser_Output_Port_B_Enc_Fid Register Field Descriptions
For Source ID 0 from Port B.. Encoder Field ID for Current Field C_FID PRTB_SRC0_PREV_ENC For Source ID 0 from Port B.. Encoder Field ID for Previous Field _FID SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 912: Vip_Parser_Output_Port_A_Src0_Size Register
On Port A.. Width of Source ID 0 15-11 Reserved 10-0 PRTA_SRC0_HEIGHT On Port A.. Height of Source ID 0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 913: Vip_Parser_Output_Port_A_Src1_Size Register
On Port A.. Width of Source ID 1 15-11 Reserved 10-0 PRTA_SRC1_HEIGHT On Port A.. Height of Source ID 1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 914: Vip_Parser_Output_Port_A_Src2_Size Register
On Port A.. Width of Source ID 2 15-11 Reserved 10-0 PRTA_SRC2_HEIGHT On Port A.. Height of Source ID 2 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 915: Vip_Parser_Output_Port_A_Src3_Size Register
On Port A.. Width of Source ID 3 15-11 Reserved 10-0 PRTA_SRC3_HEIGHT On Port A.. Height of Source ID 3 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 916: Vip_Parser_Output_Port_A_Src4_Size Register
On Port A.. Width of Source ID 4 15-11 Reserved 10-0 PRTA_SRC4_HEIGHT On Port A.. Height of Source ID 4 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 917: Vip_Parser_Output_Port_A_Src5_Size Register
On Port A.. Width of Source ID 5 15-11 Reserved 10-0 PRTA_SRC5_HEIGHT On Port A.. Height of Source ID 5 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 918: Vip_Parser_Output_Port_A_Src6_Size Register
On Port A.. Width of Source ID 6 15-11 Reserved 10-0 PRTA_SRC6_HEIGHT On Port A.. Height of Source ID 6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 919: Vip_Parser_Output_Port_A_Src7_Size Register
On Port A.. Width of Source ID 7 15-11 Reserved 10-0 PRTA_SRC7_HEIGHT On Port A.. Height of Source ID 7 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 920: Vip_Parser_Output_Port_A_Src8_Size Register
On Port A.. Width of Source ID 8 15-11 Reserved 10-0 PRTA_SRC8_HEIGHT On Port A.. Height of Source ID 8 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 921: Vip_Parser_Output_Port_A_Src9_Size Register
On Port A.. Width of Source ID 9 15-11 Reserved 10-0 PRTA_SRC9_HEIGHT On Port A.. Height of Source ID 9 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 922: Vip_Parser_Output_Port_A_Src10_Size Register
On Port A.. Width of Source ID 10 15-11 Reserved 10-0 PRTA_SRC10_HEIGHT On Port A.. Height of Source ID 10 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 923: Vip_Parser_Output_Port_A_Src11_Size Register
On Port A.. Width of Source ID 11 15-11 Reserved 10-0 PRTA_SRC11_HEIGHT On Port A.. Height of Source ID 11 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 924: Vip_Parser_Output_Port_A_Src12_Size Register
On Port A.. Width of Source ID 12 15-11 Reserved 10-0 PRTA_SRC12_HEIGHT On Port A.. Height of Source ID 12 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 925: Vip_Parser_Output_Port_A_Src13_Size Register
On Port A.. Width of Source ID 13 15-11 Reserved 10-0 PRTA_SRC13_HEIGHT On Port A.. Height of Source ID 13 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 926: Vip_Parser_Output_Port_A_Src14_Size Register
On Port A.. Width of Source ID 14 15-11 Reserved 10-0 PRTA_SRC14_HEIGHT On Port A.. Height of Source ID 14 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 927: Vip_Parser_Output_Port_A_Src15_Size Register
On Port A.. Width of Source ID 15 15-11 Reserved 10-0 PRTA_SRC15_HEIGHT On Port A.. Height of Source ID 15 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 928: Vip_Parser_Output_Port_B_Src0_Size Register
On Port B.. Width of Source ID 0 15-11 Reserved 10-0 PRTB_SRC0_HEIGHT On Port B.. Height of Source ID 0 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 929: Vip_Parser_Output_Port_B_Src1_Size Register
On Port B.. Width of Source ID 1 15-11 Reserved 10-0 PRTB_SRC1_HEIGHT On Port B.. Height of Source ID 1 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 930: Vip_Parser_Output_Port_B_Src2_Size Register
On Port B.. Width of Source ID 2 15-11 Reserved 10-0 PRTB_SRC2_HEIGHT On Port B.. Height of Source ID 2 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 931: Vip_Parser_Output_Port_B_Src3_Size Register
On Port B.. Width of Source ID 3 15-11 Reserved 10-0 PRTB_SRC3_HEIGHT On Port B.. Height of Source ID 3 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 932: Vip_Parser_Output_Port_B_Src4_Size Register
On Port B.. Width of Source ID 4 15-11 Reserved 10-0 PRTB_SRC4_HEIGHT On Port B.. Height of Source ID 4 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 933: Vip_Parser_Output_Port_B_Src5_Size Register
On Port B.. Width of Source ID 5 15-11 Reserved 10-0 PRTB_SRC5_HEIGHT On Port B.. Height of Source ID 5 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 934: Vip_Parser_Output_Port_B_Src6_Size Register
On Port B.. Width of Source ID 6 15-11 Reserved 10-0 PRTB_SRC6_HEIGHT On Port B.. Height of Source ID 6 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 935: Vip_Parser_Output_Port_B_Src7_Size Register
On Port B.. Width of Source ID 7 15-11 Reserved 10-0 PRTB_SRC7_HEIGHT On Port B.. Height of Source ID 7 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 936: Vip_Parser_Output_Port_B_Src8_Size Register
On Port B.. Width of Source ID 8 15-11 Reserved 10-0 PRTB_SRC8_HEIGHT On Port B.. Height of Source ID 8 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 937: Vip_Parser_Output_Port_B_Src9_Size Register
On Port B.. Width of Source ID 9 15-11 Reserved 10-0 PRTB_SRC9_HEIGHT On Port B.. Height of Source ID 9 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 938: Vip_Parser_Output_Port_B_Src10_Size Register
On Port B.. Width of Source ID 10 15-11 Reserved 10-0 PRTB_SRC10_HEIGHT On Port B.. Height of Source ID 10 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 939: Vip_Parser_Output_Port_B_Src11_Size Register
On Port B.. Width of Source ID 11 15-11 Reserved 10-0 PRTB_SRC11_HEIGHT On Port B.. Height of Source ID 11 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 940: Vip_Parser_Output_Port_B_Src12_Size Register
On Port B.. Width of Source ID 12 15-11 Reserved 10-0 PRTB_SRC12_HEIGHT On Port B.. Height of Source ID 12 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 941: Vip_Parser_Output_Port_B_Src13_Size Register
On Port B.. Width of Source ID 13 15-11 Reserved 10-0 PRTB_SRC13_HEIGHT On Port B.. Height of Source ID 13 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 942: Vip_Parser_Output_Port_B_Src14_Size Register
On Port B.. Width of Source ID 14 15-11 Reserved 10-0 PRTB_SRC14_HEIGHT On Port B.. Height of Source ID 14 High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 943: Vip_Parser_Output_Port_B_Src15_Size Register
On Port B.. Width of Source ID 15 15-11 Reserved 10-0 PRTB_SRC15_HEIGHT On Port B.. Height of Source ID 15 SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 944: Vip_Parser_Port_A_Vdet_Vec Register
Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 945: Vip_Parser_Port_B_Vdet_Vec Register
Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 946: Vip_Parser_Xtra2_Port_A Register
1 : Cropping module enabled 14-11 Reserved 10-0 ANC_SKIP_NUMPIX The number of pixels to crop from the beginning of each line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 947: Vip_Parser_Xtra3_Port_A Register
Reserved 10-0 ANC_SKIP_NUMLINES The number of lines to crop from the top of the vertical ancillary data region. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 948: Vip_Parser_Xtra4_Port_A Register
1 : Cropping module enabled 14-11 Reserved 10-0 ACT_SKIP_NUMPIX The number of pixels to crop from the beginning of each line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 949: Vip_Parser_Xtra5_Port_A Register
Reserved 10-0 ACT_SKIP_NUMLINES The number of lines to crop from the top of the vertical active video region. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 950: Vip_Parser_Xtra2_Port_B Register
1 : Cropping module enabled 14-11 Reserved 10-0 ANC_SKIP_NUMPIX The number of pixels to crop from the beginning of each line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 951: Vip_Parser_Xtra3_Port_B Register
Reserved 10-0 ANC_SKIP_NUMLINES The number of lines to crop from the top of the vertical ancillary data region. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 952: Vip_Parser_Xtra4_Port_B Register
1 : Cropping module enabled 14-11 Reserved 10-0 ACT_SKIP_NUMPIX The number of pixels to crop from the beginning of each line. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 953: Vip_Parser_Xtra5_Port_B Register
Reserved 10-0 ACT_SKIP_NUMLINES The number of lines to crop from the top of the vertical active video region. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 954: Vip_Parser_Xtra6_Port_A Register
If the bit position representing that srcnum is set to 0 , the port will never disable. High-Definition Video Processing Subsystem (HDVPSS) SPRUHI7A – December 2012 – Revised June 2016 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 955: Vip_Parser_Xtra7_Port_B Register
If the bit position representing that srcnum is set to 0 , the port will never disable. SPRUHI7A – December 2012 – Revised June 2016 High-Definition Video Processing Subsystem (HDVPSS) Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated...
Page 956 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.