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Texas Instruments TMS320DM643x Reference Manual

Texas Instruments TMS320DM643x Reference Manual

Digital media processor dsp subsystem
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TMS320DM643x DMP
DSP Subsystem
Reference Guide
Literature Number: SPRU978E
March 2008

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Summary of Contents for Texas Instruments TMS320DM643x

  • Page 1 TMS320DM643x DMP DSP Subsystem Reference Guide Literature Number: SPRU978E March 2008...
  • Page 2 SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Introduction Block Diagram DSP Subsystem in TMS320DM643x DMP 1.3.1 Components of the DSP Subsystem TMS320C64x+ Megamodule Introduction TMS320C64x+ CPU Memory Controllers 2.3.1 L1P Controller 2.3.2 L1D Controller 2.3.3 L2 Controller 2.3.4 External Memory Controller (EMC) 2.3.5 Internal DMA (IDMA) Internal Peripherals 2.4.1...
  • Page 4 5.3.2 Steps for Changing PLL2 Frequency PLL Controller Registers 5.4.1 Peripheral ID Register (PID) 5.4.2 Reset Type Status Register (RSTYPE) 5.4.3 PLL Control Register (PLLCTL) 5.4.4 PLL Multiplier Control Register (PLLM) 5.4.5 PLL Controller Divider 1 Register (PLLDIV1) 5.4.6 PLL Controller Divider 2 Register (PLLDIV2) 5.4.7 PLL Controller Divider 3 Register (PLLDIV3) 5.4.8...
  • Page 5 7.3.1 Module Clock ON/OFF 7.3.2 Module Clock Frequency Scaling 7.3.3 PLL Bypass and Power Down DSP Sleep Mode Management 7.4.1 DSP Sleep Modes 7.4.2 DSP Module Clock ON/OFF 3.3 V I/O Power Down Video DAC Power Down Interrupt Controller System Module Overview Device Identification Device Configuration...
  • Page 6 TMS320DM643x DMP Block Diagram TMS320C64x+ Megamodule Block Diagram C64x+ Cache Memory Architecture Overall Clocking Diagram VPBE/DAC Clocking PLL1 Structure in the TMS320DM643x DMP PLL2 Structure in the TMS320DM643x DMP Peripheral ID Register (PID) Reset Type Status Register (RSTYPE) PLL Control Register (PLLCTL)
  • Page 7 Module Status n Register (MDSTATn) Field Descriptions 6-15 Module Control n Register (MDCTLn) Field Descriptions Power Management Features TMS320DM643x DMP Master IDs TMS320DM643x DMP Default Master Priorities 10-1 Reset Types Document Revision History SPRU978E – March 2008 Submit Documentation Feedback...
  • Page 8 List of Tables SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 9: Preface

    About This Manual This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 10 TMS320C6000, C6000 are trademarks of Texas Instruments. Read This First SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 11: Introduction

    Topic Introduction Block Diagram DSP Subsystem in TMS320DM643x DMP SPRU978E – March 2008 Submit Documentation Feedback Chapter 1 SPRU978E – March 2008 Introduction Page Introduction...

  • Page 12: Introduction

    Introduction Introduction The TMS320DM643x Digital Media Processor (DMP) contains a powerful DSP to efficiently handle image, video, and audio processing tasks. The DM643x DMP consists of the following primary components and sub-systems: DSP Subsystem (DSPSS), including the C64x+ Megamodule and associated memory.

  • Page 13: Dsp Subsystem In Tms320Dm643X Dmp

    DSP Subsystem in TMS320DM643x DMP In the DM643x DMP, the DSP subsystem is responsible for performing digital signal processing for digital media applications. In addition, the DSP subsystem acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control.
  • Page 14 Introduction SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 15: Tms320C64X+ Megamodule

    Topic Introduction TMS320C64x+ CPU Memory Controllers Internal Peripherals SPRU978E – March 2008 Submit Documentation Feedback TMS320C64x+ Megamodule Chapter 2 SPRU978E – March 2008 Page TMS320C64x+ Megamodule...

  • Page 16: Introduction

    Introduction Introduction The C64x+ Megamodule (Figure TMS320C64x+ CPU Internal memory controllers: – Level-1 program memory controller (L1P controller) – Level-1 data memory controller (L1D controller) – Level-2 unified memory controller (L2 controller) – External memory controller (EMC) – Internal direct memory access (IDMA) controller Internal peripherals –...

  • Page 17: Tms320C64X+ Megamodule Block Diagram

    www.ti.com Protected mode operation: a two-level system of privileged program execution to support higher capability operating systems and system features, such as memory protection Exceptions support for error detection and program redirection to provide robust code execution Hardware support for modulo loop operation to reduce code size Industry's first assembly optimizer for rapid development and improved parallelization Figure 2-1.

  • Page 18: Memory Controllers

    Memory Controllers Memory Controllers The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1D are configurable as part L1 RAM (normal addressable on-chip memory) and part L1 cache.

  • Page 19: C64X+ Cache Memory Architecture

    www.ti.com Figure 2-2. C64x+ Cache Memory Architecture Fetch Path SRAM L1 Program L2 SRAM Legend: addressable memory cache memory data paths managed by cache controller SPRU978E – March 2008 Submit Documentation Feedback C64x+ CPU Data Path SRAM Cache L1 Data L2 Cache L2 Unified Data/Program Memory External Memory...

  • Page 20: L1D Controller

    Memory Controllers 2.3.2 L1D Controller The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D controller responds to data requests from the C64x+ CPU and manages transfer operations between L1D memory and the L2 controller and between L1D memory and the EMC.

  • Page 21: External Memory Controller (Emc)

    Refer to the internal DMA (IDMA) controller section in the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the IDMA controller and for a description of its control registers. SPRU978E – March 2008 Submit Documentation Feedback Section 3.1 and to the TMS320DM643x DMP TMS320C64x+ Megamodule Memory Controllers...

  • Page 22: Internal Peripherals

    Internal Peripherals Internal Peripherals This C64x+ Megamodule includes the following internal peripherals: Interrupt controller (INTC) Power-down controller (PDC) This section briefly describes the INTC and PDC. For more information on these peripherals, see the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871). 2.4.1 Interrupt Controller (INTC) The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts.

  • Page 23: Bandwidth Manager

    www.ti.com 2.4.3 Bandwidth Manager The bandwidth manager provides a programmable interface for optimizing bandwidth among the requesters for resources, which include the following: EDMA-initiated DMA transfers (and resulting coherency operations) IDMA-initiated transfers (and resulting coherency operations) Programmable cache coherency operations –...
  • Page 24 TMS320C64x+ Megamodule SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 25: System Memory

    Topic Memory Map Memory Interfaces Overview SPRU978E – March 2008 Submit Documentation Feedback Chapter 3 SPRU978E – March 2008 System Memory Page System Memory...

  • Page 26: Memory Map

    Memory Map Memory Map Refer to your device-specific data manual for memory-map information. 3.1.1 DSP Internal Memory (L1P, L1D, L2) This section describes the configuration of the DSP internal memory in the DM643x DMP that consists of L1P, L1D, and L2. In the DM643x DMP: L1P memory: The L1P controller allows you to configure part or all of the L1P RAM as normal program RAM or as direct mapped cache.

  • Page 27: Memory Interfaces Overview

    www.ti.com Memory Interfaces Overview This section describes the different memory interfaces of DM643x DMP. The DM643x DMP supports several memory and external device interfaces, including the following: DDR2 synchronous DRAM Asynchronous EMIF/NOR/NAND Flash 3.2.1 DDR2 External Memory Interface The DDR2 external memory interface (EMIF) port is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and can support either 16-bit or 32-bit interfaces.
  • Page 28 System Memory SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 29: Device Clocking

    Topic Overview Clock Domains SPRU978E – March 2008 Submit Documentation Feedback Chapter 4 SPRU978E – March 2008 Device Clocking Page Device Clocking...

  • Page 30: Overview

    Overview Overview The DM643x DMP requires one primary reference clock. The primary reference clock can be either crystal input or driven by external oscillators. A 27 MHZ crystal at the MXI/CLKIN pin is recommended for the system PLLs, which generate the clocks for the DSP, peripherals, DMA, and imaging peripherals. The recommended 27 MHZ input enables you to use the video DACs to drive NTSC/PAL television signals at the proper frequencies.

  • Page 31: Overall Clocking Diagram

    www.ti.com MXI/CLKIN (27 MHz) OSCDIV1 (/1) PLLDIV1 (/1) PLLDIV3 (/6) PLLDIV2 (/3) BPDIV (/1) PLL Controller 1 PCLK VPBECLK PLLDIV2 (/10) PLLDIV1 (/2) PLL Controller 2 SPRU978E – March 2008 Submit Documentation Feedback Figure 4-1. Overall Clocking Diagram AUXCLK OBSCLK (CLKOUT0 Pin) SYSCLK1 DSP Subsystem...

  • Page 32: Core Frequency Flexibility

    Clock Domains 4.2.2 Core Frequency Flexibility The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following frequency ranges and multiplier/divider ratios in the data manual must be adhered to: Input clock frequency range (MXI/CLKIN) PLL1 multiplier (PLLM) range...

  • Page 33: Ddr2/Emif Clock

    The DM643x DMP video DACs are capable of driving high quality progressive television displays, if driven by a 54 MHZ input clock sourced by PLL2 (see the TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (SPRU952) for more detailed information). This will limit the possible PLL2 settings to a multiple of 54 MHZ so that the VPBE clock can be derived with a simple integer clock divider.

  • Page 34: I/O Domains

    Clock Domains 4.2.4 I/O Domains The I/O domains refer to the frequencies of the peripherals that communicate through device pins. In many cases, there are frequency requirements for a peripheral pin interface that are set by an outside standard and must be met. It is not necessarily possible to obtain these frequencies from the on-chip clock generation circuitry, so the frequencies must be obtained from external sources and are asynchronous to the core frequency domain by definition.

  • Page 35: Video Processing Back End

    www.ti.com 4.2.5 Video Processing Back End The video processing back end (VPBE) is a submodule of the video processing subsystem (VPSS). The VPBE must interface with a variety of LCDs, as well as the 4-channel DAC module. There are many different types of LCDs, which require many different specific frequencies.

  • Page 36: Possible Clocking Modes

    Clock Domains VPSS_CLKCTL.MUXSEL Bit Clocking Mode MXI mode PLL2 mode VPBECLK mode PCLK mode Device Clocking Table 4-6. Possible Clocking Modes Description Both the VENC and the DAC get their clock from PLLC1 SYSCLKBP, which defaults to the MXI 27 MHZ crystal input divide by 1. The PLL2 (divided-down) generates a 54 MHZ clock.

  • Page 37: Pll Controller

    Topic PLL Module PLL1 Control PLL2 Control PLL Controller Registers SPRU978E – March 2008 Submit Documentation Feedback Chapter 5 SPRU978E – March 2008 PLL Controller Page PLL Controller...

  • Page 38: Pll Module

    PLL Module PLL Module The DM643x DMP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1 provides clocks (though various dividers) to most of the components of the DM643x DMP. PLL2 is dedicated to the DDR2 port and components for the video processing subsystem (VPSS). The typical reference clock is the 27 MHZ crystal input, as mentioned in The PLL controller provides the following: Glitch-Free Transitions (on changing clock settings)

  • Page 39: Device Clock Generation

    Figure 5-1. PLL1 Structure in the TMS320DM643x DMP CLKMODE CLKIN OSCIN PLLM 5.2.1 Device Clock Generation PLLC1 generates several clocks from the PLL1 output clock for use by the various processors and modules. These are summarized in frequency ratio requirement, no matter what reference clock (PLL or bypass) or PLL frequency is used.
  • Page 40 PLL1 Control 5.2.2.1 Initialization to PLL Mode from PLL Power Down If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below to change PLL1 frequencies. The recommendation is to stop all peripheral operation before changing the PLL1 frequency, with the exception of the C64x+ DSP and DDR2.
  • Page 41 www.ti.com 5.2.2.2 Changing PLL Multiplier If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section recommendation is to stop all peripheral operation before changing the PLL multiplier, with the exception of the C64x+ DSP and DDR2.
  • Page 42 PLL1 Control 5.2.2.3 Changing SYSCLK Dividers This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. The recommendation is to stop all peripheral operation before changing the SYSCLK dividers, with the exception of the C64x+ DSP and DDR2.

  • Page 43: Pll2 Control

    DDR clock is provided directly from the input reference clock. Once the PLL is powered-up and locked, software can switch the device to PLL mode operation by setting the PLLEN bit in PLLCTL to 1. Figure 5-2. PLL2 Structure in the TMS320DM643x DMP CLKMODE...

  • Page 44: Steps For Changing Pll2 Frequency

    1. Stop DDR2 memory controller accesses and purge any outstanding requests. 2. Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock. The DDR2 memory controller clock shut down sequence is in the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).
  • Page 45 12. Wait for PLL to lock. See the device-specific data manual for PLL lock time. 13. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode. For information on initializing the DDR2 memory controller, see the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).
  • Page 46 PLL2 Control 5.3.2.3 Changing PLL Multiplier If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section 1. Before changing the PLL frequency, switch to PLL bypass mode: a.
  • Page 47 www.ti.com 5.3.2.4 Changing SYSCLK Dividers This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in PLLCMD) to initiate the divider change. 1.

  • Page 48: Pll Controller Registers

    PLL Controller Registers PLL Controller Registers Table 5-3 lists the base address and end address for the PLL controllers. memory-mapped registers for the PLL and reset controller. See the device-specific data manual for the memory address of these registers. PLL and Reset Controller PLLC1 PLLC2 Offset...

  • Page 49: Peripheral Id Register (Pid)

    www.ti.com 5.4.1 Peripheral ID Register (PID) The peripheral ID register (PID) is shown in Reserved CLASS R-8h LEGEND: R = Read only; -n = value after reset Table 5-5. Peripheral ID Register (PID) Field Descriptions Field Value Description 31-24 Reserved Reserved 23-16 TYPE...

  • Page 50: Pll Control Register (Pllctl)

    PLL Controller Registers 5.4.3 PLL Control Register (PLLCTL) The PLL control register (PLLCTL) is shown in Reserved CLKMODE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5-7. PLL Control Register (PLLCTL) Field Descriptions Field Value Description...

  • Page 51: Pll Multiplier Control Register (Pllm)

    www.ti.com 5.4.4 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 5-6. PLL Multiplier Control Register (PLLM) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset For PLLC1, PLLM defaults to 10h (PLL1 multiply by 17); for PLLC2, PLLM defaults to 13h (PLL2 multiply by 20). Table 5-8.

  • Page 52: Pll Controller Divider 2 Register (Plldiv2)

    PLL Controller Registers 5.4.6 PLL Controller Divider 2 Register (PLLDIV2) The PLL controller divider 2 register (PLLDIV2) is shown in Divider 2 controls divider for SYSCLK2. Figure 5-8. PLL Controller Divider 2 Register (PLLDIV2) D2EN R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset For PLLC1, RATIO defaults to 2h (PLL1 divide by 3);...

  • Page 53: Oscillator Divider 1 Register (Oscdiv1)

    www.ti.com 5.4.8 Oscillator Divider 1 Register (OSCDIV1) The oscillator divider 1 register (OSCDIV1) is shown in oscillator divider 1 controls divider for OBSCLK, dividing down from the MXI/CLKIN clock. For PLLC1, the OBSCLK is connected to CLKOUT0 pin. OSCDIV1 only applies to PLLC1, and should not be used on PLLC2.

  • Page 54: Bypass Divider Register (Bpdiv)

    PLL Controller Registers 5.4.9 Bypass Divider Register (BPDIV) The bypass divider register (BPDIV) is shown in controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock. BPDEN R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset For PLLC1, RATIO defaults to 0 (MXI/CLKIN divide by 1);...

  • Page 55: Pll Controller Command Register (Pllcmd)

    www.ti.com 5.4.10 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) is shown in PLLCMD contains the command bit for the GO operation. Writes of 1 initiate command. Writes of 0 clear the bit, but have no effect. Figure 5-12.

  • Page 56: Pll Controller Clock Align Control Register (Alnctl)

    PLL Controller Registers 5.4.12 PLL Controller Clock Align Control Register (ALNCTL) The PLL controller clock align control register (ALNCTL) is shown in Table 5-16. ALNCTL indicates which SYSCLKs need to be aligned for proper device operation. You should not modify ALNCTL from its default settings. Figure 5-14.

  • Page 57: Plldiv Ratio Change Status Register (Dchange)

    www.ti.com 5.4.13 PLLDIV Ratio Change Status Register (DCHANGE) The PLLDIV ratio change status register (DCHANGE) is shown in Table 5-17. DCHANGE indicates if the SYSCLK divide ratio has been modified. Figure 5-15. PLLDIV Ratio Change Status Register (DCHANGE) LEGEND: R = Read only; -n = value after reset For PLLC2, SYS3 is reserved and defaults to 0.

  • Page 58: Clock Enable Control Register (Cken)

    PLL Controller Registers 5.4.14 Clock Enable Control Register (CKEN) The clock enable control register (CKEN) is shown in provides clock enable control for miscellaneous output clocks. CKEN is only applicable to PLLC1, not PLLC2. Figure 5-16. Clock Enable Control Register (CKEN) LEGEND: R/W = Read/Write;...

  • Page 59: Clock Status Register (Ckstat)

    www.ti.com 5.4.15 Clock Status Register (CKSTAT) The clock status register (CKSTAT) is shown in clock status for all clocks, except SYSCLKn. Reserved LEGEND: R = Read only; -n = value after reset For PLLC1, OBSON defaults to 1; for PLLC2, OBSON is reserved and defaults to 0. For PLLC1, AUXON defaults to 1;...

  • Page 60: Sysclk Status Register (Systat)

    PLL Controller Registers 5.4.16 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) is shown in SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the D[n]EN bit in PLLDIV[n] default. Figure 5-18. SYSCLK Status Register (SYSTAT) LEGEND: R = Read only;...

  • Page 61: Power And Sleep Controller

    Topic Introduction Power Domain and Module Topology Power Domain and Module States Executing State Transitions IcePick Emulation Support in the PSC PSC Interrupts PSC Registers SPRU978E – March 2008 Submit Documentation Feedback Power and Sleep Controller Chapter 6 SPRU978E – March 2008 Page Power and Sleep Controller...

  • Page 62: Introduction

    Introduction Introduction The Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. The DM643x DMP only utilizes the clock gating feature of the PSC for power savings. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each peripheral/module.

  • Page 63: Power Domain And Module Topology

    www.ti.com Power Domain and Module Topology The DM643x DMP includes one power domain--the AlwaysOn power domain. The AlwaysOn power domain is always on when the chip is on. The AlwaysOn domain is powered by the V DM643x DMP (see the device-specific data manual). All of the DM643x DMP modules reside within the AlwaysOn power domain.

  • Page 64: Power Domain And Module States

    Power Domain and Module States Power Domain and Module States Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire DSP.

  • Page 65: Local Reset

    www.ti.com 6.3.3 Local Reset In addition to module reset (described in reset. When DSP local reset is asserted, the DSPs internal memories (L1P, L1D, and L2) are still accessible. The local reset only resets the DSP CPU core, not the rest of the DSP subsystem, as the DSP module reset would.

  • Page 66: Icepick Emulation Support In The Psc

    IcePick Emulation Support in the PSC IcePick Emulation Support in the PSC The PSC supports IcePick commands that allow IcePick aware emulation tools to have some control over the state of power domains and modules. On the DM643x DMP, this IcePick support only applies to the C64x+ CPU (module number 39 in the AlwaysOn power domain 0).

  • Page 67: Interrupt Registers

    www.ti.com The DM643x DMP is a single-processor device. The C64x+ CPU must not program its own module state. The C64x+ CPU module state can only be programmed by an external host (for example, PCI, HPI). As a result, interrupt events listed in the C64x+ CPU module state but the emulator alters that desired state.

  • Page 68: Interrupt Handling

    PSC Registers 6.6.3 Interrupt Handling Handle the PSC interrupts as described in the following procedure: First, enable the interrupt. 1. Set the EMUIHBIE bit and the EMURSTIE bit in MDCTL39 to enable the interrupt events that you want. Note: The PSC interrupt PSCINT is sent to the DSP interrupt controller when at least one enabled event becomes active.

  • Page 69: Peripheral Revision And Class Information Register (Pid)

    www.ti.com 6.7.1 Peripheral Revision and Class Information Register (PID) The peripheral revision and class information (PID) register is shown in Table 6-6. Figure 6-2. Peripheral Revision and Class Information Register (PID) SCHEME Reserved R-4h LEGEND: R = Read only; -n = value after reset Table 6-6.

  • Page 70: Module Error Pending Register 1 (Merrpr1)

    PSC Registers 6.7.3 Module Error Pending Register 1 (MERRPR1) The module error pending register 1 (MERRPR1) is shown in the C64x+ CPU (module 39) can have an error condition, as it is the only module with IcePick support. Section 6.5 for more information.

  • Page 71: Power Domain Transition Command Register (Ptcmd)

    www.ti.com 6.7.5 Power Domain Transition Command Register (PTCMD) The power domain transition command register (PTCMD) is shown in Table 6-10. Figure 6-6. Power Domain Transition Command Register (PTCMD) LEGEND: R = Read only; W = Write only; -n = value after reset Table 6-10.

  • Page 72: Power Domain Status 0 Register (Pdstat0)

    PSC Registers 6.7.7 Power Domain Status 0 Register (PDSTAT0) The power domain status n register (PDSTAT0) is shown in PDSTAT0 applies to the AlwaysOn power domain. Figure 6-8. Power Domain Status 0 Register (PDSTAT0) Reserved LEGEND: R = Read only; -n = value after reset Table 6-12.

  • Page 73: Power Domain Control 0 Register (Pdctl0)

    www.ti.com 6.7.8 Power Domain Control 0 Register (PDCTL0) The power domain control n register (PDCTL0) is shown in PDCTL0 applies to the AlwaysOn power domain. Figure 6-9. Power Domain Control 0 Register (PDCTL0) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-13.

  • Page 74: Module Status N Register (Mdstatn)

    PSC Registers 6.7.9 Module Status n Register (MDSTATn) The module status n register (MDSTAT0-MDSTAT39) is shown in Table 6-14. Figure 6-10. Module Status n Register (MDSTATn) Reserved MCKOUT Reserved LEGEND: R = Read only; -n = value after reset Table 6-14. Module Status n Register (MDSTATn) Field Descriptions Field Value Description...

  • Page 75: Module Control N Register (Mdctln)

    www.ti.com 6.7.10 Module Control n Register (MDCTLn) The module control n register (MDCTL0-MDCTL39) is shown in Figure 6-11. Module Control n Register (MDCTLn) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-15. Module Control n Register (MDCTLn) Field Descriptions Field Value Description...
  • Page 76 Power and Sleep Controller SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 77: Power Management

    Topic Overview PSC and PLLC Overview Clock Management DSP Sleep Mode Management 3.3 V I/O Power Down Video DAC Power Down SPRU978E – March 2008 Submit Documentation Feedback Chapter 7 SPRU978E – March 2008 Power Management Page Power Management...

  • Page 78: Overview

    Leakage power can only be avoided by removing power completely from a device or subsystem. The TMS320DM643x DMP has several means of managing the power consumption, as detailed in the following sections. There is extensive use of automatic clock gating in the design as well as software-controlled module clock gating to not only reduce the clock tree power, but to also reduce module power by basically freezing its state while not operating.

  • Page 79: Clock Management

    www.ti.com Clock Management 7.3.1 Module Clock ON/OFF The module clock on/off feature allows software to disable clocks to module individually, in order to reduce the module's active power consumption to 0. The DM643x DMP is designed in full static CMOS; thus, when a module clock stops, the module's state is preserved.

  • Page 80: Dsp Sleep Mode Management

    DSP Sleep Mode Management DSP Sleep Mode Management The C64x+ DSP supports sleep mode management to reduce power: DSP clock can be completely shut off C64x+ Megamodule can be put in sleep mode – C64x+ CPU can be put in sleep mode On the DM643x DMP, sleep mode for the DSP internal memories (L1P, L1D, L2) is not supported.

  • Page 81: I/O Power Down

    4 DACs to a low level, regardless of the video signal. Furthermore, you can use the DAPD[3:0] bits in DACTST to disable each DAC independently. See the TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (SPRU952) for register descriptions and more detailed information on DAC power-down.
  • Page 82 Power Management SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 83: Interrupt Controller

    The C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The interrupt controller interfaces the system events to the CPU's interrupt and exception inputs. The interrupt controller supports up to 128 system events, and it maps these system events to the 12 CPU interrupts. See the device-specific data manual for the list of system events.
  • Page 84 Interrupt Controller SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 85: System Module

    Topic Overview Device Identification Device Configuration 3.3 V I/O Power-Down Control Peripheral Status and Control Bandwidth Management Boot Control SPRU978E – March 2008 Submit Documentation Feedback Chapter 9 SPRU978E – March 2008 System Module Page System Module...

  • Page 86: Overview

    Overview Overview The TMS320DM643x DMP System Module is a system-level module containing status and top-level control logic required by the device. The System Module consists of a set of status and control registers, accessible by the DSP, supporting all of the following system features and operations:...

  • Page 87: I/O Power-Down Control

    The DDR2 VTP Enable Register (DDRVTPER) is used along with other registers in the VTP IO buffer calibration process for the DDR2 memory controller. See the device-specific data manual for the location of this register. See the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986) for more details on the VTP IO buffer calibration process.

  • Page 88: Bandwidth Management

    ID (mstid) associated with it. The master ID for each DM643x DMP master is shown Table 9-1. MSTID 11-15 22-31 33-35 39-63 System Module Table 9-1. TMS320DM643x DMP Master IDs Master Reserved DSP Program / Data DSP CFG Reserved VPSS Reserved EDMA Channel Controller...

  • Page 89: Edma Transfer Controller Configuration

    Control Registers (MSTPRI0 or MSTPRI1). The default priority level for each bus master is shown in Table 9-2. Application software is expected to modify these values to obtain the desired system performance. Table 9-2. TMS320DM643x DMP Default Master Priorities Master VPSS EDMA Ch 0...
  • Page 90 System Module SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 91: Reset

    Topic 10.1 Overview 10.2 Reset Pins 10.3 Device Configurations at Reset 10.4 DSP Reset SPRU978E – March 2008 Submit Documentation Feedback Chapter 10 SPRU978E – March 2008 Reset Page Reset...

  • Page 92: Overview

    Overview 10.1 Overview There are different types of reset in the TMS320DM643x DMP. The types of reset differ by how they are initiated and/or by their effect on the chip. Each type is briefly described in device-specific data manual for more details on each of the reset types.

  • Page 93: Dsp Reset

    www.ti.com 10.4 DSP Reset Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire DSP. With access to the power and sleep controller (PSC) registers, the external host (for example, PCI or HPI) can assert and de-assert DSP local reset and DSP module reset.
  • Page 94 DSP Reset Host: Assert the DSP local reset (Optional) – Clear the LRST bit in MDCTL39 to 0. This step is optional. This step asserts the DSP local reset, and is included here so that the DSP does not start running immediately upon it is subsequently enable by the host.

  • Page 95: Boot Modes

    The TMS320DM643x DMP can boot from either asynchronous EMIF/NOR Flash directly or from internal boot ROM, as determined by the setting of the device boot and configuration pins. The input states of the boot and configuration pins are sampled and latched into the BOOTCFG register when device reset is deasserted.
  • Page 96 Boot Modes SPRU978E – March 2008 Submit Documentation Feedback...

  • Page 97: A Revision History

    Table A-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Figure 6-1 Added Note. Section 6.3 Added Note. Section 10.4 Added Note. SPRU978E – March 2008 Submit Documentation Feedback Table A-1. Document Revision History Appendix A SPRU978E –...

  • Page 98: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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