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Texas Instruments MSP50C6xx User Manual

Texas Instruments MSP50C6xx User Manual

Mixed-signal processor
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MSP50C6xx Mixed-Signal Processor
User's Guide
Mixed Signal Products
SPSU014A
Printed on Recycled Paper

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Summary of Contents for Texas Instruments MSP50C6xx

  • Page 1 MSP50C6xx Mixed-Signal Processor User’s Guide Mixed Signal Products SPSU014A Printed on Recycled Paper...
  • Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.

  • Page 3: Read This First

    About This Manual This user’s guide gives information for the MSP50C6xx mixed-signal proces- sor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer informa- tion, and electrical characteristics (in data sheet).
  • Page 4 Notational Conventions Here is a sample program listing: 0011 0005 0012 0005 0013 0005 0014 0006 Here is an example of a system prompt and a command that you might enter: C: csr –a /user/ti/simuboard/utilities In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface.
  • Page 5 .byte value This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas. Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.

  • Page 7: Table Of Contents

    Introduction to the MSP50C6xx Features of the MSP50C6xx Applications ..............
  • Page 8 Contents Peripheral Functions .............
  • Page 9 ..............MSP50C6xx Development Tools Guidelines 5.2.1...
  • Page 10 ............Initializing the MSP50C6xx 6.2.1...
  • Page 11 ..............2–1 MSP50C6xx Core Processor Block Diagram 2–2 Computational Unit Block Diagram 2–3...
  • Page 12 Tables Tables 2–1 Signed and Unsigned Integer Representation 2–2 Summary of MSP50C614’s Peripheral Communications Ports 2–3 Programmable Bits Needed to Control Reduced Power Modes 2–4 Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3) 2–5 How to Wake Up from Reduced Power Modes (Refer to Table 2–3 and Table 2–4) 2–6 Destination of Program Counter on Wake-Up Under Various Conditions 3–1...
  • Page 13 4–28 Class 6a Instruction Encoding 4–29 Class 6a Instruction Description 4–30 Class 6b Instruction Description 4–31 Class 7 Instruction Encoding and Description 4–32 Class 8a Instruction Encoding 4–33 Class 8a Instruction Description 4–34 Class 8b Instruction Description 4–35 Class 9a Instruction Encoding 4–36 Class 9a Instruction Description 4–37...

  • Page 15: Introduction To The Msp50C6Xx

    Introduction to the MSP50C6xx The MSP50C6xx is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose input/output (I/O), onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the MSP50C6xx unprecedented speed and computational flexibility compared with previous devices of its type.

  • Page 16: Features Of The Msp50C6Xx

    Resistor-trimmed oscillator or 32.768-kHz crystal reference oscillator Serial scan port for in-circuit emulation and diagnostics The MSP50C6xx is sold in die form or QFP package. An emulator device, MSP50P614 is sold in a ceramic package for development. The MSP50P614 devices operate from 4.0 Vdc to 6.0 Vdc, and...

  • Page 17: Applications

    1.2 Applications Due to its low cost, low-power consumption, and high programmability, the MSP50C6xx is suitable for a wide variety of applications incorporating flexible I/O and high-quality speech: Consumer Toys and Games Appliances Talking Clocks Navigation Aids Industrial Warning Systems Controls...

  • Page 18: Development Device: Msp50P614

    Note: The MSP50P614 operates with a voltage range of 4 V to 6 V. However, the MSP50C6xx devices operate at a different voltage range (3 V to 5.2 V). Please refer to the data sheet for specific device information.

  • Page 19: Functional Description For The Msp50C614

    Control Interrupt Processor FLAG MASK 0x39 0x38 F port INPUT Data DMAU Data Mem. Addr. G port OUTPUT 0x000 to Data 0x027F Introduction to the MSP50C6xx PA0–7 0x00 0x04 PB0–7 0x08 0x0C PC0–7 0x10 0x14 – PD0–7 0x18 0x1C PE0–7...
  • Page 20 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are re- served by Texas Instruments for a built-in self-test, 2) the upper 30K is for user program/data. The data memory is internal static RAM. The RAM is configured in 640 17-bit words.

  • Page 21: Oscillator And Pll Connection

    I/O ports. Functional Description for the MSP50C614 MSP50P614 MSP50C6xx OSCOUT 10 M † 32.768 kHz† 22 pF† 22 pF† C (PLL) = 3300 pF† MSP50C6xx MSP50P614 OSCOUT C (PLL) = 3300 pF† ports bit-wise programmable Introduction to the MSP50C6xx either...

  • Page 22: Reset Circuit

    An external reset circuit is required to hold the reset pin low until the MSP50C6xx power supply has stabilized in the specified voltage range. In some cases, a simple reset circuit (as shown in Figure 1–3) can be used for this purpose.

  • Page 23: Msp50C601, Msp50C604, And Msp50C605

    1.5 MSP50C601, MSP50C604, and MSP50C605 Related products, the MSP50C601, MSP50C604, and MSP50C605 use the MSP50C6xx core. The MSP50C601 has a 128K byte data ROM built into the chip and 32 I/O port pins. The MSP50C605 has a 224K byte data ROM built into the chip and 32 I/O port pins.
  • Page 24 1-10...

  • Page 25: Msp50C6Xx Architecture

    MSP50C6xx Architecture A detailed description of the MSP50C6xx architecture is included in this chap- ter. After reading this chapter, the reader will have in-depth knowledge of inter- nal blocks, memory organization, interrupt system, timers, clock control mech- anism, and various low power modes.

  • Page 26: Architecture Overview

    2.1 Architecture Overview The core processor in the C6xx is a medium performance mixed signal proces- sor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accumulator-register file provides additional scratch pad memory and mini- mizes memory thrashing for many operations.

  • Page 27: Msp50C6Xx Core Processor Block Diagram

    Figure 2–1. MSP50C6xx Core Processor Block Diagram Multiplier (MR)† Shift Value (SV)† 17 x 17 Multiplier Product High (PH)† 16 bit ALU 32 Accumulators (AC0–AC31)† Column Exchange Stack (R7) Page (R6) Index (R5) Loop (R4) Arithmetic Unit Data Memory 640 x 17 bit †...

  • Page 28: Computational Unit Block Diagram

    Figure 2–2. Computational Unit Block Diagram Shift Value (SV) Multiplier Register (MR) 17 bit x 17 bit Multiplexer Product High (PH) Accumulators Internal Databus – 16 bit (Product Low, PL) 16 LSB 16 MSB Read/Write AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23...

  • Page 29: Computation Unit

    Refer to Figure 2–3 for an overview of this operation. At the end of the current execution cycle, the upper word (MSB) of the product is latched into the product high register (PH). Signed Decimal 0xFFFF 0xFFFF 0x8000 32768 0x8000 0x7FFF 32767 0x7FFF 0x0000 0x0000 MSP50C6xx Architecture Computation Unit...
  • Page 30 Computation Unit The multiplicand source can be either data memory, an accumulator, or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register. For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift value register (SV).

  • Page 31: Arithmetic Logic Unit

    - writeable and readable by Data Memory as one of the following ... MULTIPLYING: (MR) Multiplier Register† SHIFTING: (SV) Shift Value Register MULTIPLIER UNIT LSB 16-bit (PL) Product Low - a simulated register: PL is realized in ALU-A MSP50C6xx Architecture Computation Unit 16-bit 4-bit...
  • Page 32 Computation Unit The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are useful for supporting multiply-accumulate operations (refer to Section 2.2.1, Multiplier).

  • Page 33: Overview Of The Arithmetic Logic Unit

    ALU-B 16-bit - selects between ... all 0’s Accumulator Register ARITHMETIC LOGIC UNIT ALU OUTPUTS OFFSET Accumulator Register 16-bit registers ... AC16, AC17, AC18, AC19, AC20, AC21, AC22, AC23, AC24, AC25, AC26, AC27, AC28, AC29, AC30, AC31 MSP50C6xx Architecture Computation Unit...

  • Page 34: Overview Of The Accumulators

    Computation Unit When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C6xx instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of the actual 16-bit accumulator.

  • Page 35: Data Memory Address Unit

    (R4), the INDEX register (R5), the PAGE register (R6), and the STACK register (R7). The DMAU generates a RAM address as output. The DMAU functions completely in parallel with the computational unit, which helps the C6xx maintain a high computational throughput. MSP50C6xx Architecture 2-11...

  • Page 36: Ram Configuration

    Data Memory Address Unit Figure 2–6. Data Memory Address Unit Internal Databus 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for op-codes in the instruction set.

  • Page 37: Data Memory Addressing Modes

    The effective RAM address is: [*Rx + (a 16 bit direct offset)]. Refer to Chapter 4, Assembly Language Instructions, for a full description of how these modes are used in conjunction with various instructions. Data Memory Address Unit MSP50C6xx Architecture 2-13...

  • Page 38: Program Counter Unit

    Program Counter Unit 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops).

  • Page 39: Memory Organization: Ram And Rom

    The memory map for the C6xx is shown in Figure 2–7. Refer to Section 2.6.3, Interrupt Vectors, for more detailed information regarding the interrupt vectors, and to Section 2.6.2, Peripheral Communications (Ports), for more information on the I/O communications ports. Memory Organization: RAM and ROM MSP50C6xx Architecture 2-15...

  • Page 40: Peripheral Communications (Ports)

    Memory Organization: RAM and ROM Figure 2–7. C6xx Memory Map (not drawn to scale) Program Memory 0x0000 Internal Test Code 2048 x 17 bit (reserved) 0x07FF 0x0800 User ROM 30704 x 17 bit (C6xx : read-only) (P614 : EPROM) 0x7F00 Macro Call Vectors 255 x 17 bit (overlaps interrupt...

  • Page 41: Summary Of Msp50C614'S Peripheral Communications Ports

    Output port G data PG 0..15 Data RTO oscillator trim RTRIM adjustment DAC data DAC Data DAC control DAC Ctrl Interrupt/general Ctrl IntGenCtrl MSP50C6xx Architecture State after Section for RESET LOW Reference unknown† 0x00 ‡ unknown 0x00 unknown 3.1.1 0x00...

  • Page 42: Interrupt Vectors

    Memory Organization: RAM and ROM Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued) I/O Map Width of Allowable Address Location Access 0x39 8 bits Read & Write 0x3A 16 bits Read & Write 0x3B 16 bits Read & Write 0x3D 16 bits Write Only...

  • Page 43: Rom Code Security

    The two-block system is designed in such a way that a secondary developer is prevented from changing the partition address between blocks. Once the block protection has been engaged, then the only security option available to the secondary developer is engaging the global protection. Memory Organization: RAM and ROM MSP50C6xx Architecture 2-19...
  • Page 44 Memory Organization: RAM and ROM Note: Instructions with References Care must be taken when employing instructions that have either long string constant references or look-up table references. These instructions will execute properly only if the address of the instruction and the address of the data reference are within the same block.
  • Page 45 Note: Block Protection Word The remaining bits in the block protection word are reserved for future use, but must remain set in order to ensure future compatibility. These bits are numbers 6, 15, and 16. Memory Organization: RAM and ROM MSP50C6xx Architecture 2-21...

  • Page 46: Macro Call Vectors

    Interrupt Logic When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an inter- nal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended.
  • Page 47 Peripheral Communications (Ports), for more information.) (8-bit wide location) D4 PF high priority priority PF : any port F falling-edge T2 : TIMER2 underflow T1 : TIMER1 underflow DA : DAC timer underflow MSP50C6xx Architecture Interrupt Logic INT number 2-23...
  • Page 48 Interrupt Logic Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain- ing a software interrupt. An IFR bit may also be cleared, using OUT, at any time.

  • Page 49: Interrupt Initialization Sequence

    INT3 INT2 INT Mask bits (IMR) Specific Enable for Interrupt Service Interrupt / General Control Register (0x38)† INT7 INT6 INT5 INT4 INT3 INT2 0x7FF2 0x7FF4 0x7FF6 0x7FF3 0x7FF5 0x7FF7 MSP50C6xx Architecture Interrupt Logic SET BIT INT1 INT0 INT1 INT0 2-25...

  • Page 50: Clock Control

    Clock Control In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered.
  • Page 51 1 ... x 256 Timer Source Option Selected in IntGenCtrl crystal referenced Master Clock : Runs Periphery 131.07 kHz ... 33.554 MHz CPU Clock Core-Processor Speed 65.536 kHz ... F MAX (F MAX = 8 MHz) MSP50C6xx Architecture Clock Control TIMER2 TIMER2 2-27...

  • Page 52: Clock Speed Control Register

    Clock Control 2.8.3 Clock Speed Control Register The ClkSpdCtrl is a 16-bit memory mapped register located at address 0x3D. The reference oscillator (RTO or CRO) is selected by setting one of the two control bits located at bits 8 and 9. Setting bit 8 configures the C6xx for the RTO reference option and simultaneously starts that oscillator.

  • Page 53: Rto Oscillator Trim Adjustment

    For the C6xx parts, the correct trim value is located at I/O location 0x2Fh. I C or T0 R R : enable Resistor-trimmed oscillator M : PLLM multiplier bits for MC 0x0000 : default state after RESET LOW MSP50C6xx Architecture Clock Control 2-29...
  • Page 54 ClkSpdCtrl Value Copied (Shaded) When selecting and enabling the RTO oscillator,therefore, the bits at positions 05 through 01 should be read from I/O location 0x2F (MSP50C6xx device only), then copied to the ClkSpdCtrl trim adjust (bits 15 through 11 of control register 0x3D), and bit 0 of 0x2F I/O port should be copied to bit 9 of ClkSpdCtrl register.

  • Page 55: Timer Registers

    0x0000 : default state of both registers after RESET LOW † TIMER1 may be associated with the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details. and OSC MSP50C6xx Architecture Timer Registers . Also, note that this Triggers INT1 on underflow...
  • Page 56 Timer Registers Reading from either the PRD or the TIM returns the current state of the register. This can be used to monitor the progress of the TIM register at any time. Writing to the PRD register does not change the TIM register until the TIM register has finished decrementing to 0x0000.

  • Page 57: Reduced Power Modes

    The performance and flexibility of the reduced power modes make the C6xx ideal for battery powered operation. Refer to data sheets for the MSP50C6xx devices. The reduced power state on the C6xx is achieved by a call to the IDLE instruction.
  • Page 58 Reduced Power Modes overall power consumption during that state. The various subsystems that determine (or are affected by) the depth of sleep include the: Processor core, which is driven by the CPU clock PLL clock circuitry PLL reference oscillator C6xx periphery, which is driven by the master clock TIMER1 and TIMER2 PDM pulsing The deepest sleep achievable on the C6xx, for example, is a mode where all...
  • Page 59 PLL clock circuitry is stopped in sleep (by virtue of the idle state control). The disadvantage of the asynchronous response, however, is that it can render irregularities in the timing of response to these same inputs. MSP50C6xx Architecture 2-35...

  • Page 60: Programmable Bits Needed To Control Reduced Power Modes

    Reduced Power Modes Note: Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bit is clear, the only event that can wake the C6xx after an IDLE instruction is a hardware RESET low- to-high.

  • Page 61: Status Of Circuitry When In Reduced Power Modes (Refer To Table 2-3)

    A, E running stopped B, F 131 kHz 34 MHz C, E Synchronous Asynchronous stopped stopped running stopped A, B, E running running MSP50C6xx Architecture Reduced Power Modes DEEP stopped stopped stopped — — Asynchronous stopped stopped stopped 2-37...

  • Page 62: How To Wake Up From Reduced Power Modes (Refer To Table 2-3 And Table 2-4)

    Reduced Power Modes either type of interrupt (internal or external). In most cases, the state of these bits should coincide. The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep.

  • Page 63: Destination Of Program Counter On Wake-Up Under Various Conditions

    Program counter goes to the next instruction immediately following the IDLE which initiated sleep. Wake-up cannot occur from the programmed Interrupt under these conditions. If RESET low-to-high occurs, then program goes to the location stored in the RESET interrupt vector. MSP50C6xx Architecture Reduced Power Modes 2-39...

  • Page 64: Execution Timing

    Execution Timing 2.11 Execution Timing For executing program code, the C6xx’s core processor has a three-level pipeline. The pipeline consists of instruction fetch, instruction decode, and instruction execution. A single instruction cycle is limited to one program Fetch plus one data memory read or write. The master clock consists of two phases with non-overlap protection.

  • Page 65: Peripheral Functions

    Peripheral Functions This chapter describes in detail the MSP50C6xx peripheral functions, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, compara- tor and digital-to-analog (DAC) control mechanisms. Topic I/O ............

  • Page 66: I/O

    3.1 I/O This section discusses the I/O capabilities of the MSP50C6xx family. The fol- lowing table shows the number and types of I/O available on each device. Please note that this section discusses all I/O ports, which are only available on the MSP50C614 device.
  • Page 67 Port A † Control register address 0x04h Possible control values 0 = High-Z INPUT Value after RESET low Data register address 0x00h Possible input data values Low = 0 Possible output data values † Each of these I/O ports is only 8 bits wide. The reason for the 4-byte address spacing is so that with limited addressability (such as memory transfers) can still access instructions these registers.

  • Page 68: Dedicated Input Port F

    The following table shows the bit locations of the I/O port mapping: A port data register A port control register B port data register B port control register C port data register C port control register D port data register D port control register E port data register E port control register...

  • Page 69: Dedicated Output Port G

    and setting the EP bit enables the eight pullups. After RESET low, the default setting for the EP bit is 0 (F-port pullups disabled). Possible output data values When reading from the 8-bit F-port data register to a 16-bit accumulator, the IN instruction automatically clears the extra bits in excess of 8.

  • Page 70: Branch On D Port

    The following table shows the bit locations of the port G address mapping: G port Data address 0x2C (16-bit wide location) read and write G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 3.1.4 Branch on D Port Instructions exist to branch conditionally depending upon the state of ports D...

  • Page 71: Internal And External Interrupts

    In a deep-sleep state, they can also be used to wake the device when used in conjunction with the ARM bit. Please refer to Section 2.11, Reduced Power Modes, for information regarding the MSP50C6xx’s reduced power modes. Peripheral Functions...

  • Page 72: Interrupts

    A summary of the interrupts is given in Table 3–1. Table 3–1. Interrupts Interrupt Vector Source Trigger Event INT0 0x7FF0 DAC Timer Timer underflow INT1 0x7FF1 TIMER1 Timer underflow INT2 0x7FF2 TIMER2 Timer underflow INT3 0x7FF3 Rising edge INT4 0x7FF4 Falling edge †...

  • Page 73: Digital-To-Analog Converter (Dac)

    There are four sampling rates which may be used effectively within the constraints of the MSP50C6xx and the various software vocoders provided by Texas Instruments. These are: 7.2 kHz, 8 kHz, 10 kHz, and 11.025 kHz. Other sampling rates, however, may also be possible.
  • Page 74 Digital-to-Analog Converter (DAC) DAC Control register Address 0x34 Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits: DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DAC enable) 0x0 : default state of register after RESET low Bit 2 in the DAC control register is used to enable/disable the pulse-density...

  • Page 75: Pdm Clock Divider

    style. Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style. The overflow bits appear in the DAC data register (14 and 13) to the left of the MSB data bit (12).
  • Page 76 PLLM and the resulting MC rate. The column in these tables output sampling rate reports the true audio sampling rate achievable by the MSP50C6xx, using the 32.768-kHz CRO. The values reported are not always exact multiples of the 8-kHz and 10-kHz options;...
  • Page 77 Example 3–1. 8-kHz Sampling Rate ClkSpdCtrl PLLM IntGenCtrl Over- Register Value PDMCD Sampling Factor (hex) Precision 8 bits 0x 0F 0x 1E 0x 3E 0x 7C 0x 1E 0x 3E 0x 7C 9 bits 0x 1E 0x 3E 0x 7C 0x 3E 0x 7C 10 bits...
  • Page 78 Digital-to-Analog Converter (DAC) Example 3–2. 10-kHz Sampling Rate 32.768 kHz Oscillator Reference ClkSpdCtrl PLLM Register IntGenCtrl Over- PDMCD Sampling Value Precision Factor (hex) 8 bits 0x 13 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 9 bits 0x 26 0x 4D 0x 9B...

  • Page 79: Comparator

    3.3 Comparator The MSP50C6xx provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD . PD is the noninverting input to the comparator, and PD input. When the comparator is enabled, the conditional operation COND2 (normally...

  • Page 80: Relationship Between Comparator/Interrupt Activity And The Timer1 Control

    Comparator The INT6 Flag may also be SET or CLEARed deliberately, at any time, in software. Use the OUT instruction with the associated I/O port address (IFR, address 0x39). INT7 flag refers to bit 7 within the interrupt flag register. This bit is automatically SET anytime that an INT7 event occurs.
  • Page 81 The function of pins PD INT7, and TIMER1 are different, depending on whether the comparator has been enabled or disabled. A summary of the various states appears in the fol- lowing table: Comparator ENABLED functions as comparator negative input functions as comparator positive input COND2 maps to the state of the comparator INT6 is triggered by PD rising above PD...

  • Page 82: Interrupt/General Control Register

    Interrupt/General Control Register 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The IMR is used to individually enable all interrupts except RESET.
  • Page 83 Bit 14 is the ARM bit. If the master clock has been suspended during sleep, then the ARM bit must be set (before the IDLE instruction), in order to allow a programmable interrupt to wake the MSP50C6xx. Refer to Section 2.11, Reduced Power Modes, for more information.

  • Page 84: Hardware Initialization States

    (refer to the MSP50C6xx data sheet (SPSS023), Electrical Specifications sec- tion). When the RESET pin is held low, the MSP50C6xx is considered reset and has the following internal states: RESET low . . .
  • Page 85 Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power. This applies also to the interrupt flag register. The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, many of the programmable controls and registers are left in their default states: RESET high, just after low .

  • Page 86: State Of The Status Register (17 Bit) After Reset Low-To-High

    Hardware Initialization States Table 3–2. State of the Status Register (17 bit) after RESET Low-to-High (Bits 5 through 16 are left uninitialized) Bit Name Initialized Value (reserved) Same state as before RESET 3-22 Description Extended sign mode disabled Unsigned multiplier mode disabled (allows signed multiplier mode) Overflow mode disabled (allows ALU normal mode) Shift mode for fractional multiplication disabled (allows unsigned fractional/integer arithmetic)

  • Page 87: Assembly Language Instructions

    Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described. Topic Introduction ..........System Registers .

  • Page 88: Introduction

    Introduction 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding.

  • Page 89: Top Of Stack, (Tos)

    or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction.

  • Page 90: Product High Register (Ph)

    System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only. 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32-bit result of a multiplication, multiply-accumulate, or shift operation.

  • Page 91: Accumulator Pointers (Ap0–Ap3)

    During accumulator read operations, both An and offset An~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumulator (An or An~) is the least significant word (LSW) of the string and is restored at the end of the operation.

  • Page 92: String Register (Str)

    System Registers value of the STACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used.

  • Page 93: Status Register (Stat)

    Table 4–1. Status Register (STAT) Name Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6.

  • Page 94: Msp50P614/Msp50C614 Instruction Syntax

    Instruction Syntax and Addressing Modes 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destination arguments. In the following subsec- tion, a detail of the MSP50P614/MSP50C614 instruction syntax is explained followed by the subsection which describes addressing modes.

  • Page 95: Addressing Modes

    4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, di- rect, indirect with post modification, and three relative modes. The relative modes are: Relative to the INDEX or R5 register. The effective address is (indirect reg- ister + INDEX). Short relative to the PAGE or R6 register.

  • Page 96: Addressing Mode Bits And {Adrs} Field Description

    Instruction Syntax and Addressing Modes Table 4–3. Rx Bit Description Table 4–4. Addressing Mode Bits and {adrs} Field Description Relative Relative Clocks Words Addressing Operation Modes Modes † Direct Short relative Relative to R5 † Long relative Indirect † = dma16 and offset16 is the second word ‡...

  • Page 97: Msp50P614/Msp50C614 Addressing Modes Summary

    Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX Direct name [dest,] [src,] *dma16 [*2] [, next A] name *dma16 [*2] [,src] [, next A] Long Relative name [dest] [,src] ,*Rx+offset16 [, next A] name *Rx+offset16 [,src] [, next A] Relative to R5 name [dest] [,src] ,*Rx+R5 [, next A] (INDEX) name *Rx+R5 [,src] [, next A]...

  • Page 98: Flag Addressing Field {Flagadrs} For Certain Flag Instructions (Class 8A)

    Instruction Syntax and Addressing Modes For any particular addressing mode, replace the {adrs} with the syntax shown in Table 4–4. To encode the instruction, replace the am, Rx and pm bits with the bits required by the addressing mode (Table 4–4). For example, the instruction MOV An[~], {adrs} [, next A] combinations are shown):...

  • Page 99: Immediate Addressing

    4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax: name dest, [src,] imm [, next A] Where: imm is the immediate value of a 16-bit number.

  • Page 100: Direct Addressing

    Instruction Syntax and Addressing Modes 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax: name [dest,] [src,] *dma16 [* 2] [, next A] name *dma16 [* 2] [, src] [, next A] Memory Operand Note the multiplication by 2 with the data memory address.

  • Page 101: Indirect Addressing Syntax

    4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications, the register increments or decrements itself by 2 for word operands and by 1 for byte operands.

  • Page 102: Relative Addressing

    Instruction Syntax and Addressing Modes Example 4.3.12 Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5.
  • Page 103 Example 4.3.17 Refer to the initial processor state in Table 4–8 before execution of this instruc- tion. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDed with AC2. The result is stored in AC2. The val- ues in R3 and R5 are unchanged.
  • Page 104 Instruction Syntax and Addressing Modes Example 4.3.20 Refer to the initial processor state in Table 4–8 before execution of this instruc- tion. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 Refer to the initial processor state in Table 4–8 before execution of this instruc- tion.

  • Page 105: Relative Flag Addressing

    4.3.7 Flag Addressing This addressing mode addresses only the 17 data memory. This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various logical operations can be performed without affecting the re- maining 16 bits of the selected word.

  • Page 106: Tag/Flag Bits

    Instruction Syntax and Addressing Modes 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. The TAG bit is the 17 each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614. When an instruction of the format, MOV accumulator, RAM is performed, the STAT register is affected by various properties of this trans-...
  • Page 107 However, xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle. Possible sources of confusion: Consider the following code, ram0 equ0x0000 *2 ;RAM word zero ram1 equ0x0001 *2 ;RAM word one ram2 equ0x0002 *2 ;RAM word two STAG...

  • Page 108: Symbols And Explanation

    Instruction Classification 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory, hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within the class, and the abbreviated field descriptions.

  • Page 109: Instruction Classification

    Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [next A] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers An or An~. NOT condition on conditional jumps, conditional calls or test flag instructions. Value in the repeat counter loaded by repeat instruction.
  • Page 110 Instruction Classification Table 4–11. Instruction Classification (Continued) Class Sub- Description Class Register and memory reference Memory references that use Rx; all addressing modes available Memory references with short constant fields operating on Rx Memory references with long constant fields operating on Rx in errata, has not been connected Memory references with R5 operating on Rx General mMemory reference instructions I/O port and memory reference instructions...

  • Page 111: Classes And Opcode Definition

    Table 4–12. Classes and Opcode Definition Class 1a Class 1b Class 2a Class 2b Class 3 Class 4a Class 4b Class 4c Class 4d Class 5 Class 6a Class 6b Class 7a Class 7b JMP *An Class 7c CALL *An Class 8a Class 8b Class 9a...

  • Page 112: Class 1 Instruction Encoding

    Instruction Classification Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory. Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A bit.

  • Page 113: Class 1B Instruction Description

    Table 4–15. Class 1b Instruction Description Mnemonic OR An, {adrs} ORS An, {adrs} AND An, {adrs} ANDS An, {adrs} XOR An, {adrs} XORS An, {adrs} MOVB An, {adrs} MOVBS An, {adrs} MOVB {adrs} , An MOVBS {adrs} , An Reserved CMP An, {adrs} CMPS An, {adrs} MOV {adrs} , *An...

  • Page 114: Class 2 Instructions: Accumulator And Constant Reference

    Instruction Classification Table 4–15. Class 1b Instruction Description (Continued) Mnemonic MULAPL An, {adrs} MULAPLS An, {adrs} SHLTPL An, {adrs} SHLTPLS An, {adrs} SHLSPL An, {adrs} SHLSPLS An, {adrs} SHLAPL An, {adrs} SHLAPLS An, {adrs} MULSPL An, {adrs} MULSPLS An, {adrs} 4.4.2 Class 2 Instructions: Accumulator and Constant Reference These instructions provide the capability to reference short (8 bits) or long (16...

  • Page 115: Class 2 Instruction Encoding

    constants. Long constants (16 bits) and long string constants differ in that ref- erences are made to constants in the second word of the two-word instruction word. References made to a single 16-bit integer constant are immediate. That is, the actual constant value follows the first word opcode in memory. For string constants, the second word reference to the constants is immediate-indirect which indicates that the second word is the address of the least significant word of the string constant.

  • Page 116: Class 3 Instruction: Accumulator Reference

    Instruction Classification Table 4–18. Class 2b Instruction Description Mnemonic 0 ADD An[~], An[~], imm16 [, next A] ADDS An[~], An[~], pma16 1 MOV An[~], imm16 [, next A] MOVS An[~], pma16 0 SUB An[~], An[~], imm16 [, next A] SUBS An[~], An[~], pma16 1 CMP An[~], imm16 [, next A] CMPS An[~], pma16 0 OR An[~], An[~], imm16 [, next A]...

  • Page 117: Class 3 Instruction Encoding

    between the accumulator and the MR, SV, or PH register. As with all accumula- tor referenced instructions, string operations are possible as well as premodi- fication of one of 4 indirectly referenced accumulator pointer registers (AP). Table 4–19. Class 3 Instruction Encoding Class 3 Table 4–20.
  • Page 118 Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) Mnemonic 0 1 0 0 0 XOR An[~], An~, An [, next A] XORS An[~], An~, An 0 1 0 0 1 OR An[~], An~, An [, next A] ORS An[~], An~, An 0 1 0 1 0 AND An[~], An~, An [, next A] ANDS An[~], An~, An 0 1 0 1 1 SHRAC An[~], An[~] [, next A]...
  • Page 119 Table 4–20. Class 3 Instruction Description (Continued) Mnemonic 1 0 1 0 0 MOV SV, An[~] [, next A] MOVS SV, An[~] 1 0 1 0 1 MOV PH, An[~] [, next A] MOVS PH, An[~] 1 0 1 1 0 MOV MR, An[~] [, next A] MOVS MR, An[~] 1 0 1 1 1 MOVU MR, An[~] [, next A] 1 1 0 0 0 MULSPL An[~], An[~] [, next A]...

  • Page 120: Class 4 Instructions: Address Register And Memory Reference

    Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) Mnemonic 1 1 1 1 0 MUL An[~] [, next A] MULS An[~] 1 1 1 1 1 SHL An[~] [, next A] SHLS An[~] 4.4.4 Class 4 Instructions: Address Register and Memory Reference Class 4 instructions operate on the indirect register, Rx, that exists in the ad- dress unit (ADU).

  • Page 121: Class 4A Instruction Description

    Table 4–22. Class 4a Instruction Description Mnemonic Description MOV {adrs}, Rx Store Rx register to data memory referred by addressing mode {adrs}. Modify transfer status. MOV Rx, {adrs} Load Rx with the value in data memory referred by addressing mode {adrs}. Modify transfer status.

  • Page 122: Class 5 Instructions: Memory Reference

    Instruction Classification 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), the shift value register (SV), the status register (STAT), the top of stack (TOS), the string register (STR), and the four accumulator pointer registers AP0 to AP3.
  • Page 123 Table 4–27. Class 5 Instruction Description (Continued) Mnemonic Description 0 1 0 1 MOV {adrs}, TOS Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode {adrs}. Transfer status is modified. 0 1 1 0 STAG {adrs} Store 1 to the 17...

  • Page 124: Class 6 Instructions: Port And Memory Reference

    Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) Mnemonic Description 1 1 1 1 RPT {adrs} Load repeat counter with lower 8 bits of data memory location referred by addressing mode {adrs}. Interrupts are queued during execution. 1 1 1 1 MOV STAT, {adrs} Load status (STAT) register with effective data memory location referred by addressing mode {adrs} (17 bits with TAG).

  • Page 125: Class 7 Instructions: Program Control

    Table 4–30. Class 6b Instruction Description Mnemonic Description IN An[~], port6 Transfer the port’s 16-bit value to an accumulator. Port addresses 0–63 INS An[~], port6 are valid. ALU status is modified. OUT port6, An[~] Transfer a 16-bit accumulator value to the addressed port. Port address- OUTS port6, An[~] es 0–63 are valid.

  • Page 126: Class 7 Instruction Encoding And Description

    Instruction Classification Table 4–31. Class 7 Instruction Encoding and Description VCALL vector8 JMP *An CALL *An cc names cc name Not cc name REZI RLZI 4-40 Description Conditional on ZF=1 Conditional on SF=1 Conditional on CF=1 Conditional on ZF=0 and CF=0 Conditional on ZF=0 and CF=1 Conditional on SF=0 and ZF=0 Conditional if ZF=1 and OF=0...

  • Page 127: Class 8 Instructions: Logic And Bit

    Table 4–31. Class 7 Instruction Encoding and Description (Continued) cc names cc name Not cc name 4.4.8 Class 8 Instructions: Logic and Bit This class of instructions provides a flexible and efficient means to make complex logical decisions. Instead of making a sequence of single bit decisions and constructing a logical statement through a branch decision tree, the program can sequentially combine several status conditions to directly construct a final logic value (TF1 or TF2) which can be used to control a...

  • Page 128: Class 9 Instructions: Miscellaneous

    Instruction Classification Table 4–33. Class 8a Instruction Description Mnemonic Description MOV TFn, {flagadrs} Load flag bit (17 {flagadrs} to either TF1 or TF2 in status register. Load with inverted value if Not =1. OR TFn, {flagadrs} Logically OR either TF1 or TF2 with flag bit (17 referred by flag addressing mode {flagadrs} (or inverted value if N=1) addressed by the instruction and store back to TF1 or TF2 respectively.

  • Page 129: Class 9A Instruction Encoding

    Table 4–35. Class 9a Instruction Encoding Class 9a Class 9b Class 9c Class 9d ENDLOOP n Table 4–36. Class 9a Instruction Description Mnemonic Description FIRK An, *Rx Finite impulse response tap execution. When used with repeat counter will execute a 16 bit 16 bit multiplication between an indirect-addressed data memory buffer and program memory (coefficients).

  • Page 130: Class 9C Instruction Description

    Bit, Byte, Word and String Addressing Table 4–38. Class 9c Instruction Description Mnemonic Description MOV APn, imm6 Load the accumulator pointer (AP) with a 5-bit constant. ADD APn, imm5 Add a 5-bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39. Class 9d Instruction Description Mnemonic Description 0 0 0 0 BEGLOOP...

  • Page 131: Data Memory Organization And Addressing

    is a string of bytes. The length of the byte string is stored in the string register (STR). To define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8.

  • Page 132: Data Memory Address And Data Relationship

    Bit, Byte, Word and String Addressing Flag Address: The flag (or TAG) address uses linear addressing from 0 to the size of data memory in 17-bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17 is read, the corresponding flag for that location is always loaded into the TAG bit of the status register (STAT).

  • Page 133: Data Memory Example

    Figure 4–4. Data Memory Example Absolute Word Data Memory Location (even) = 2 * (Absolute word memory location) Memory Location 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 Example 4.5.4 Refer to Figure 4–4 for this example. The byte-string length is 4. It is loaded to the string register (STR) in the first instruction.
  • Page 134 Bit, Byte, Word and String Addressing Example 4.5.7 Refer to Figure 4–4 for this example. The word-string length is 4. AP0 points to AC2 accumulator. R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002. R0 autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2.

  • Page 135: Msp50P614/Msp50C614 Computational Modes

    Example 4.5.10 Refer to Figure 4–4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded with 0 (string length of 2). The second instruction sets the flag bit to 1 at flag address 0x0032.

  • Page 136: Msp50P614/Msp50C614 Computational Modes

    MSP50P614/MSP50C614 Computational Modes Table 4–41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Instruction Mode Instruction Sign extension Unsigned none none Overflow SOVM ROVM Fractional Sign Extension Mode: Sign extension mode can be enabled/disabled by setting/resetting the XM bit of STAT. When in sign extension mode, a multiply operation will copy the 16 When multiplied, this will give a 17 x 17 bit multiplication producing 34-bit result where the upper two bits (33...
  • Page 137 MSP50P614/MSP50C614 Computational Modes Example 4.6.2 MOV STR, 2–2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication.
  • Page 138 MSP50P614/MSP50C614 Computational Modes Example 4.6.1 In this example, we set the overflow mode (OM = 1 of STAT). Adding 0x7FFE with 5 causes an overflow (OF = 1 of STAT). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF.

  • Page 139: Hardware Loop Instructions

    Hardware Loop Instructions high word of the result is stored in the PH register and is 0x3FFF. The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fraction- al numbers (all bits are to the right of the decimal point), then the result will be a Q30 number.

  • Page 140: Hardware Loops In Msp50P614/Msp50C614

    Hardware Loop Instructions the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to control the hardware repeat count, it is not possible to nest repeats and strings.

  • Page 141: Initial Processor State For String Instructions

    4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators (N is the length of the string).
  • Page 142 String Instructions A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3–2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF, AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry. Special String Sequences: There are two string instructions that have a special meaning.

  • Page 143: Lookup Instructions

    4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, characters for an LCD display which can be read for display in the LCD screen, etc.
  • Page 144 Lookup Instructions Lookup instructions make use of the data pointer (DP) internally. The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after the execution of lookup instructions.

  • Page 145: Fir Filter Structure

    4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and the accumulators. Data input is performed with the IN instruction (Class 6).
  • Page 146 Special Filter Instructions N tap filters ideally require 2N multiply–accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instruction.
  • Page 147 theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circu- lar buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the circular buffer and the filter coefficients.
  • Page 148 Special Filter Instructions After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so The second detail is the STAT register.
  • Page 149 A0,*nextSample ;Replace last sample with newest sample *R0,A0 ; and update the start of the *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer. Wrap around happens automatically. This tells the processor how many words to step back when the end of the circular buffer is reached.
  • Page 150 Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction. 0x0106 Use R5 to wrap around 0x0100 After FIR/COR execution The STAT register is saved in the filterSTAT_tag location. The output of the fil- tering operation in the example is located in AC0 (lower word) and AC1 (high word).
  • Page 151 Important Note About Setting the STAT Register It is very important to consider the initial value of the filterSTAT_tag variable. Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit of the STAT register may not be set.
  • Page 152 Special Filter Instructions firk movs The set up for the FIRK/CORK instruction is the same as the set up for the FIR/ COR instruction with the exception that the filter coefficients do not need to be loaded into RAM locations. Rather, they can be included just before speech data or elsewhere in the program code as follows, FIRK_COEFFS include...

  • Page 153: Setup And Execution Of Msp50P614/Msp50C614 Filter Instructions, N+1 Taps

    Figure 4–6. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps coeff_array address even coeff_array address {R1,R3,R5,R7} even sample_buf address {R0,R2,R4,R6} Circular buffer operation only Circular buffer length, –2N Accumulators Pointer An = ACn Point to accumulator, ACr TAG=1 for 2 Accumulators 0–15 bits of y...

  • Page 154: Filter Instruction And Circular Buffering For N+1 Tap Filter

    Special Filter Instructions Figure 4–7. Filter Instruction and Circular Buffering for N+1 Tap Filter CORK/FIRK only coeff_array coeff_array COR/FIR only even 16 Bits coeff_array h[0] h[1] h[2] h[3] h[4] h[N–1] h[N] coeff_array is stored in program or data memory based on filter instruction. program memory (FIRK/CORK) data memory (FIR/COR) AC n+2...

  • Page 155: Conditionals

    4.12 Conditionals The condition bits in the status register (STAT) are used to modify program control through conditional branches and calls. Various combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register.

  • Page 156: Legend

    Legend 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [dest] [, src] [, src1] [, mod] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instruction. Optional for some instructions or not used.
  • Page 157 Symbol Meaning Select offset accumulator as the source if this bit is 1. Used in opcode encoding only. Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encod- ing only. Select offset accumulator as the source if this bit is 0. Used in opcode encoding only. Can be either ~A or A~ based on opcode (or instruction).
  • Page 158 Legend Symbol Meaning Value in repeat counter loaded by RPT instructions Value in string register STR Overflow flag offset[n] n bit offset from a reference register. Overflow mode Program counter, 16 bits pma[n] n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16.

  • Page 159: Auto Increment And Decrement

    Table 4–45. Auto Increment and Decrement Operation next A No modification Auto increment Auto Decrement – –A Table 4–46. Addressing Mode Bits and adrs Field Description Relative Clocks Words Addressing Addressing Modes Direct Short relative Relative to R5 Long relative Indirect Indirect †...

  • Page 160: Individual Instruction Descriptions

    Individual Instruction Descriptions 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions. Each instruction is discussed in detail and provides the following information: Assembler syntax Clock cycles required with or without repeat instructions...
  • Page 161 4.14.1 ADD Add word Syntax [label] name dest, src [, src1] [,mod] An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5 †...
  • Page 162 Individual Instruction Descriptions Description Syntax Description ADD dest, src ADD src with dest and store the result to dest. ADD dest, src, src1 [,mod] ADD src1 with src and store the result to dest. Premodify the mod before execution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Example 4.14.1.1...
  • Page 163 4.14.2 ADDB ADD BYTE Syntax [label] name dest, src ADDB An, imm8 ADDB Rx, imm8 Execution dest dest + src PC + 1 Flags Affected dest is An: dest is Rx: Opcode Instructions ADDB An imm5 ADD Rx, imm8 See Also ADD, ADDS, SUB, SUBB, SUBS Description Add immediate value of unsigned src byte to value stored in dest register and...
  • Page 164 Individual Instruction Descriptions 4.14.3 ADDS Add String Syntax [label] name dest, src, src1 ADDS An[~], An, {adrs} ADDS An[~], An[~], pma16 ADDS An[~], An~, An ADDS An[~], An[~], PH † † This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multi- ply or shift operation as if the sequence was a single string.
  • Page 165 Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1~, put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0.
  • Page 166 Individual Instruction Descriptions 4.14.4 AND Bitwise AND Syntax [label] name dest, src [, src1] [, mod] An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, [!]{flagadrs} TFn, {cc} [, Rx] Execution [premodify AP if mod specified] dest dest AND src dest...
  • Page 167 See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation. Example 4.14.4.2 AND A0~, A0, 0xff0f, –...
  • Page 168 Individual Instruction Descriptions 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src ANDB An, imm8 Execution dest dest AND src byte PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions ANDB An, imm8 Description Bitwise AND src byte and byte stored in dest register and store result in dest register.
  • Page 169 4.14.6 ANDS Bitwise AND String Syntax [label] name dest, src [, src1] ANDS An, {adrs} ANDS An[~], An[~], pma16 ANDS An[~], An~, An Execution dest string dest string PC + w Flags Affected dest is An: src is {adrs}: Opcode Instructions ANDS An, {adrs} ANDS An[~], An[~], pma16...
  • Page 170 Individual Instruction Descriptions 4.14.7 BEGLOOP Begin Loop Syntax [label] name † BEGLOOP † Loop must end with ENDLOOP. Execution Save next instruction address (PC + 1) (mask interrupts) PC + 1 Flags Affected none Opcode Instructions BEGLOOP Description This instruction saves the next sequential address in a shadow register and masks interrupts.
  • Page 171 4.14.8 CALL Unconditional Subroutine Call Syntax [label] name address CALL pma16 CALL Execution R7 + 2 PC + 2 *An or pma16 Flags Affected None Opcode Instructions CALL pma16 CALL *An † The value of An is in the following table. Bit 9 Bit 8 Description...
  • Page 172 Individual Instruction Descriptions Note: You can not RET to a RET. For example, the following code can cause prob- lems: CALL my sub To eliminate any problem, a NOP (or other code) should be inserted between the CALL and the RET. For example: CALL my sub 4-86...
  • Page 173 4.14.9 Ccc Conditional Subroutine Call Syntax [label] name address † pma16 † Cannot immediately follow a CALL instruction with a return instruction. If true [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label] [label]...

  • Page 174: Names For Cc

    Individual Instruction Descriptions Table 4–48. Names for cc cc names cc name Not cc name 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1...
  • Page 175 Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP. A Ccc instruction cannot be followed by a return (RET) instruction.
  • Page 176 Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF = 1 CRNC pma16 Conditional call on RCF = 0 CRE pma16 CRZ pma16 Conditional call on RZF = 1 (equal) CRNE pma16 CRNZ pma16 Conditional call on RZF = 0 (not equal) CXG pma16 CXNLE pma16 Conditional call on transfer greater (signed)
  • Page 177 4.14.10 CMP Compare Two Words [label] name src, src1 [, mod] An, {adrs} An[~], imm16 [, next A] An, An~ [, next A] An~, An [, next A] † Rx, imm16 † Rx, R5 † Does not modify An status Execution [premodify AP if mod specified] STAT flags set by src –...
  • Page 178 Individual Instruction Descriptions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly. 4-92...
  • Page 179 4.14.11 CMPB Compare Two Bytes Syntax [label] name src, src1 CMPB An, imm8 CMPB Rx, imm8 Execution status flags set by src – src1 byte PC + 1 Flags Affected src is An: src is Rx: Opcode Instructions CMPB An, imm8 CMPB Rx, imm8 Description Subtract value of src1 (zero filled in upper 8 bits) from src (i.e., src–src1) and...
  • Page 180 Individual Instruction Descriptions 4.14.12 CMPS Compare Two Strings Syntax [label] name src, src1 CMPS An, {adrs} CMPS An[~], pma16 CMPS An, An~ CMPS An~, An Execution status flags set by (src – src1) string PC + w Flags Affected src is An: src1 is {adrs}: Opcode Instructions...
  • Page 181 4.14.13 COR Correlation Filter Function Syntax [label] name dest, src An, *Rx Execution With RPT N–2: (mask interrupts) RPT counter = N–2 MR = h[0] = first filter coefficient x = sample data pointed by Rx h[1] = second filter coefficient pointed by Rx y = result stored in three consecutive accumulators (48 bit) pointed by An {between every accumulation} IF TAG = 1...
  • Page 182 Individual Instruction Descriptions 4.14.14 CORK Correlation Filter Function Syntax [label] name dest, src CORK An, *Rx Execution With RPT N–2: (mask interrupts) RPT counter = N–2 MR = h[0] = first filter coefficient x = sample data pointed at by Rx h[1] = second filter coefficient pointed by DP y = result stored in three consecutive accumulators (48 bit) pointed by An {between every accumulation}...
  • Page 183 4.14.15 ENDLOOP End Loop Syntax [label] name ENDLOOP Execution If (R4 decrement R4 by n (1 or 2) first address after BEGLOOP else PC + 1 Flags Affected None Opcode Instructions ENDLOOP n Description This instruction marks the end of a loop defined by BEGLOOP. If register R4 is not negative, R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP.
  • Page 184 Individual Instruction Descriptions 4.14.16 EXTSGN Sign Extend Word Syntax [label] name dest [, mod] An[~] [, next A] EXTSGN Execution [premodify AP if mod specified] new most significant word of dest PC + 1 Flags Affected None Opcode Instructions EXTSGN An[~] [, next A] Description Copy accumulator sign flag (SF) to all 16 bits of An[~].
  • Page 185 4.14.17 EXTSGNS Sign Extend String Syntax [label] name dest An[~] EXTSGNS Execution new most significant word of dest PC + 1 Flags Affected None Opcode Instructions EXTSGNS An[~] Description Extend the sign bit (SF) of most significant word an additional 16 bits to the left. The accumulator address is preincremented (internally) causing the sign of the addressed accumulator to be extended into the next accumulator address.
  • Page 186 Individual Instruction Descriptions MOV AP1, 3 MOVS A0, *R0 EXTSGN A1 Alternatively, the following code can do the same thing but requires more code: MOV AP0, 0 MOV AP1, 3 ZAC A1 MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY JNS POSITIVE ;...
  • Page 187 4.14.18 FIR FIR Filter Function (Coefficients in RAM) Syntax [label] name dest, src An, *Rx Execution With RPT N–2: (mask interrupts) RPT counter = N–2 MR = h[0] = first filter coefficient x = sample data pointed at by Rx h[1] = second filter coefficient pointed at Rx y = result stored in three consecutive accumulators (32 bit) pointed by An {between every accumulation}...
  • Page 188 Individual Instruction Descriptions See Also RPT, FIRK, COR, CORK Example 4.14.18.1 RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data. 4-102...
  • Page 189 4.14.19 FIRK FIR Filter Function (Coefficients in ROM) Syntax [label] name dest, src FIRK An, *Rx Execution With RPT N–2: (mask interrupts) RPT counter = N–2 MR = h[0] = first filter coefficient x = sample data pointed by Rx h[1] = second filter coefficient pointed by DP y = result stored in three consecutive accumulators (32 bit) pointed by An [between every accumulation}...
  • Page 190 Individual Instruction Descriptions 4.14.20 IDLE Halt Processor Syntax [label] name IDLE Execution Stop processor clocks PC + 1 Flags Affected None Opcode Instructions IDLE Description Halts execution of processor. An external interrupt wakes the processor. This instruction is the only instruction to enter one of the three low power modes defined in section 2.11.
  • Page 191 4.14.21 IN Input From Port Into Word Syntax [label] name dest, src1 {adrs}, port4 An[~], port6 Execution dest content of port6 or port4 PC + w Flags Affected dest is An: dest is {adrs} Opcode Instructions IN {adrs}, port4 IN An[~], port6 Description Input from I/O port.
  • Page 192 Individual Instruction Descriptions 4.14.22 INS Input From Port Into String Syntax [label] name src, src1 An[~], port6 Execution dest content of port6 PC + 1 Flags Affected dest is An: Opcode Instructions INS An[~], port6 Description Input string from same port, port6, to accumulator string. Strings can be input to accumulators from one of 64 port addresses.

  • Page 193: Interrupt Disable

    4.14.23 INTD Interrupt Disable Syntax [label] name INTD Execution STAT.IM PC + 1 Flags Affected None Opcode Instructions INTD Description Disables interrupts. Resets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 0. See Also INTE, IRET Example 4.14.23.1 INTD Disable interrupts.

  • Page 194: Interrupt Enable

    Individual Instruction Descriptions 4.14.24 INTE Interrupt Enable Syntax [label] name INTE Execution STAT.IM PC + 1 Flags Affected None Opcode Instructions INTE Description Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 1. See Also INTD, IRET Example 4.1 INTE...

  • Page 195: Return From Interrupt

    4.14.25 IRET Return From Interrupt Syntax [label] name IRET Execution R7 – 2 Flags Affected None Opcode Instructions IRET See Also RET, CALL, Ccc, INTE, INTD Description Return from interrupt. Pop top of stack to program counter. Example 4.1 IRET Return from interrupt service routine.
  • Page 196 Individual Instruction Descriptions 4.14.26 Jcc Conditional Jumps Syntax [label] name pma16 [, Rmod] pma16 [, Rmod] If true [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label] pma16 [, Rmod] [label]...
  • Page 197 Opcode Instructions Jcc pma16 Jcc pma16 Rx++ Jcc pma16 Rx–– Jcc pma16, Rx++R5 cc names cc name Not cc name RNZP RLZP RNLZP NTF1 NTF2 NTAG NIN1 NIN2 Individual Instruction Descriptions pma16 pma16 pma16 pma16 Description Description True condition (Not true condition) Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0)
  • Page 198 Individual Instruction Descriptions cc names cc name Not cc name Description PC is replaced with second word operand if condition is true (or unconditional). If test condition is false, a NOP is executed. Syntax Alternate Instruction JA pma16 [, Rmod] JNBE JNA pma16 [, Rmod] JB pma16 [, Rmod]...
  • Page 199 Syntax Alternate Instruction JRNLZP pma16 [, Rmod] JRZP pma16 [, Rmod] JRNZP pma16 [, Rmod] JS pma16 [, Rmod] JNS pma16 [, Rmod] JTAG pma16 [, Rmod] JNTAG pma16 [, Rmod] JTF1 pma16 [, Rmod] JNTF1 pma16 [, Rmod] JTF2 pma16 [, Rmod] JNTF2 pma16 [, Rmod] JXG pma16 [, Rmod] JXNLE...
  • Page 200 Individual Instruction Descriptions 4.14.27 JMP Unconditional Jump Syntax [label] name dest [, mod] pma16 pma16, Rx++ pma16, Rx– – pma16, Rx++R5 Execution dest [Post–modify Rx if specified] Flags Affected RCF and RZF affected by post–modification of Rx Opcode Instructions JMP pma16 JMP pma16 Rx++ JMP pma16...
  • Page 201 4.14.28 MOV Move Data Word From Source to Destination Syntax [label] name dest, src, [, next A] {adrs}, An[~] [, next A] An[~], {adrs} [, next A] {adrs}, *An An[~], imm16 [, next A] MR, imm16 [, next A] An, An~ [, next A] An[~], PH [, next A] SV, An[~] [, next A] PH, An[~] [, next A]...
  • Page 202 Individual Instruction Descriptions [label] name dest, src, [, next A] TFn, {cc} [, Rx] STR, imm8 SV, imm4 APn, imm5 Execution [premodify AP if mod specified] dest PC + w Flags Affected dest is An: dest is Rx: dest is {adrs}: src is {adrs} src is {flagadrs} Opcode...
  • Page 203 Instructions MOV Rx, R5 MOV SV, imm4 MOV SV, {adrs} 4 MOV PH, {adrs} MOV MR, {adrs} MOV APn, {adrs} MOV STAT, {adrs} MOV TOS, {adrs} MOV {adrs}, PH MOV {adrs}, MR MOV {adrs}, STAT MOV {adrs}, STR MOV {adrs}, DP MOV {adrs}, SV MOV {adrs}, APn MOV {adrs}, TOS...
  • Page 204 Individual Instruction Descriptions Description Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types. Syntax MOV An[~], {adrs} [, next A] MOV {adrs}, An[~] [, next A] MOV An[~], imm16 [, next A] MOV MR, imm16 [, next A] MOV An, An~ [, next A] MOV An~, An [, next A] MOV An[~], PH [, next A]...
  • Page 205 Syntax MOV STR, imm8 MOV APn, imm5 † Accumulator condition flags are modified to reflect the value loaded into either An or An~. ‡ Signed multiplier mode resets UM (bit 1 in status register) to 0 ¶ Load the logic value of the test condition to the TFn bit in the status register (STAT). If the condition is true, TFn=1, else TFn=0. See Also MOVU, MOVT, MOVB, MOVBS, MOVS Example 4.14.28.1...
  • Page 206 Individual Instruction Descriptions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word location 0x0200.
  • Page 207 4.14.29 MOVAPH Move With Adding PH Syntax [label] name dest, src, src1 MOVAPH An, MR, {adrs} Execution An + PH contents of {adrs} PC + w Flags Affected TAG, OF, SF, ZF, CF are set accordingly Opcode Instructions MOVAPH An, MR, {adrs} Description Move RAM word to MR register, add PH to An in parallel.
  • Page 208 Individual Instruction Descriptions 4.14.30 MOVAPHS Move With Adding PH Syntax [label] name dest, src, src1 MOVAPHS An, MR, {adrs} Execution An + PH contents of {adrs} PC + w Flags Affected TAG, OF, SF, ZF, CF are set accordingly Opcode Instructions MOVAPHS An, MR, {adrs} Description...
  • Page 209 4.14.31 MOVB Move Byte From Source to Destination Syntax [label] name dest, src MOVB An, {adrs} MOVB {adrs}, An MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8 Execution dest PC + w Flags Affected dest is An: dest is Rx: dest is {adrs}: src is {adrs} Opcode...
  • Page 210 Individual Instruction Descriptions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal).
  • Page 211 4.14.32 MOVBS Move Byte String from Source to Destination Syntax [label] name dest, src MOVBS An, {adrs} MOVBS {adrs}, An Execution dest PC + w Flags Affected dest is An: dest is {adrs}: src is {adrs} Opcode Instructions MOVBS An, {adrs} 8 MOVBS {adrs} 8 , An Description Copy value of src byte to dest.
  • Page 212 Individual Instruction Descriptions 4.14.33 MOVS Move String from Source to Destination Syntax [label] name dest, src MOVS An[~], {adrs} MOVS {adrs}, An[~] MOVS {adrs}, *An MOVS An[~], pma16 † MOVS An[~], PH MOVS An, An~ MOVS An[~], *An[~] † Certain restriction applies to the use of this instruction when interrupts are occuring on the background. See Section 4.8 for more detail.
  • Page 213 Description Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types. Syntax Description MOVS An[~], {adrs} Move data memory word string to An[~] string MOVS {adrs}, An[~] Move An[~] string to data memory MOVS {adrs}, *An Move program memory string at *An to data memory MOVS An[~], pma16...
  • Page 214 Individual Instruction Descriptions 4.14.34 MOVSPH Move With Subtract from PH Syntax [label] name dest, src, src1 MOVSPH An, MR, {adrs} Execution An – PH contents of {adrs} PC + w Flags Affected TAG, OF, SF, ZF, CF are set accordingly Opcode Instructions MOVSPH An, MR, {adrs}...
  • Page 215 4.14.35 MOVSPHS Move String With Subtract From PH Syntax [label] name dest, src, src1 MOVSPHS An, MR, {adrs} Execution An (second word) – PH contents of {adrs} PC + w Flags Affected TAG, OF, SF, ZF, CF are set accordingly Opcode Instructions MOVSPHS An, MR, {adrs}...
  • Page 216 Individual Instruction Descriptions 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src MOVT {adrs}, TFn Execution dest PC + w Flags Affected None Opcode Instructions MOVT {adrs}, TFn Description Move TFn from STAT register to memory tag. All addressing modes are available.
  • Page 217 4.14.37 MOVU Move Data Unsigned Syntax [label] name dest, src [, mod] MOVU MR, An[~] [, next A] MOVU MR, {adrs} Execution [premodify AP if mod specified] dest PC + w Flags Affected src is {adrs} UM is set to 1 Opcode Instructions MOVU MR, An[~] [, next A]...

  • Page 218: Valid Moves/Transfer In Msp50P614/Msp50C614 Instruction Set

    Individual Instruction Descriptions Figure 4–8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set MR/SV Immediate NOTE: B = Byte move possible. S = String move possible. R5 can be moved to Rx, An[–] to An[–] 4-132 xxxxxx xxxx00 Flag Bit STAT...
  • Page 219 4.14.38 MUL Multiply (Rounded) Syntax [label] name src [, mod] An[~] [, next A] {adrs} Execution [premodify AP if mod specified] PH,PL MR * src PC + w Flags Affected src is An : src is {adrs}: Opcode Instructions MUL An[~] [, next A] MUL {adrs} Description Multiply MR and src.
  • Page 220 Individual Instruction Descriptions 4.14.39 MULR Multiply (Rounded) With No Data Transfer Syntax [label] name MULR {adrs} Execution PH,PL MR * src PC + 1 Flags Affected TAG bit is set accordingly Opcode Instructions MULR [adrs] Description Perform multiplication of multiply register (MR) and effective data memory value, add 08x00 to the product.
  • Page 221 4.14.40 MULS Multiply String With No Data Transfer Syntax [label] name MULS An [~] Execution PH,PL MR * src string PC + 1 Flags Affected None Opcode Instructions MULS An[~] Description Multiply MR and the value in src. The 16 MSBs of the ( (n are stored in the PH register.
  • Page 222 Individual Instruction Descriptions 4.14.41 MULAPL Multiply and Accumulate Result Syntax [label] name dest, src [, mod] MULAPL An, {adrs} MULAPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH,PL MR * src dest dest + PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}:...
  • Page 223 4.14.42 MULAPLS Multiply String and Accumulate Result Syntax [label] name dest, src [, mod] MULAPLS An, {adrs} MULAPLS An[~], An[~] Execution PH,PL MR * src dest dest + PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs} : Opcode Instructions...
  • Page 224 Individual Instruction Descriptions 4.14.43 MULSPL Multiply and Subtract PL From Accumulator Syntax [label] name dest, src [, mod] MULSPL An, {adrs} MULSPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH,PL MR * src dest dest – PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly...
  • Page 225 4.14.44 MULSPLS Multiply String and Subtract PL From Accumulator Syntax [label] name dest, src MULSPLS An, {adrs} MULSPLS An[~], An[~] Execution PH,PL MR * src dest dest – PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode Instructions...
  • Page 226 Individual Instruction Descriptions 4.14.45 MULTPL Multiply and Transfer PL to Accumulator Syntax [label] name dest, src [, mod] MULTPL An, {adrs} MULTPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH,PL MR * src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}:...
  • Page 227 4.14.46 MULTPLS Multiply String and Transfer PL to Acumulator Syntax [label] name dest, src MULTPLS An, {adrs} MULTPLS An[~], An[~] Execution PH, PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode Instructions MULSPLS An, {adrs} MULSPL S An[~], An[~] Description...
  • Page 228 Individual Instruction Descriptions 4.14.47 NEGAC Two’s Complement Negation of Accumulator Syntax [label] name dest, src [,mod] NEGAC An[~], An[~] [, next A] Execution [premodify AP if mod specified] dest –src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions NEGAC An[~], An[~] [, next A]...
  • Page 229 4.14.48 NEGACS Two’s Complement Negation of Accumulator String Syntax [label] name dest, src NEGACS An[~], An[~] Execution dest –src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions MULSPL S An[~], An[~] Description Perform two’s complement negation of src accumulator string and store result in dest accumulator string.
  • Page 230 Individual Instruction Descriptions 4.14.49 NOP No Operation Syntax [label] name Execution PC + 1 Flags Affected None Opcode Instructions Description This instruction performs no operation. It consumes 1 clock of execution time and 1 word of program memory. See Also Example 4.14.49.1 Consumes 1 clock cycle.
  • Page 231 4.14.50 NOTAC One’s Complement Negation of Accumulator Syntax [label] name dest, src [, mod] NOTAC An[~], An[~] [, next A] Execution [premodify AP if mod specified] dest NOT src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions NOTAC An[~], An[~] [, next A]...
  • Page 232 Individual Instruction Descriptions 4.14.51 NOTACS One’s Complement Negation of Accumulator String Syntax [label] name dest, src NOTACS An[~], An[~] Execution dest NOT src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions NOTACS An[~], An[~] Description Perform one’s complement of src accumulator string and store result in dest accumulator string.
  • Page 233 4.14.52 OR Bitwise Logical OR Syntax [label] name dest, src [, src1] [, mod] An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx] Execution [premodify AP if mod specified] dest dest OR src1 dest...
  • Page 234 Individual Instruction Descriptions See Also ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS Example 4.14.52.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0, Add R5 to R0 after execution. Example 4.14.52.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1.
  • Page 235 4.14.53 ORB Bitwise OR Byte Syntax [label] name dest, src An, imm8 Execution dest dest OR src PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions ORB An, imm8 Description Bitwise OR byte of src and dest. Result is stored in dest. Only lower 8 bits of accumulator is affected.
  • Page 236 Individual Instruction Descriptions 4.14.54 ORS Bitwise OR String Syntax [label] name dest, src [, src1] An, {adrs} An[~], An[~], pma16 An[~], An~, An Execution dest dest OR src (for two operands) dest src1 OR src (for three operands) PC + w Flags Affected dest is An: src is {adrs}:...
  • Page 237 4.14.55 OUT Output to Port Syntax [label] name dest, src port4, {adrs} port6, An[~] Execution port4 or port6 PC + w Flags Affected XSF, XZF are set accordingly src is {adrs}: Opcode Instructions OUT port4, {adrs} OUT port6, An[~] Description Output to I/O port.
  • Page 238 Individual Instruction Descriptions 4.14.56 OUTS Output String to Port Syntax [label] name dest, src OUTS port6, An[~] Execution port6 PC + 1 Flags Affected XSF, XZF are set accordingly Opcode Instructions OUTS port6, An[~] Description Output to I/O port. Word in the accumulator string can be output to one of 64 port addresses.
  • Page 239 4.14.57 RET Return From Subroutine (CALL, Ccc) Syntax [label] name Execution R7 – 2 Flags Affected None Opcode Instructions Description Return from call or vectored call. Pop stack to program counter, continue execution. Returns from subroutine calls (CALL, Ccc instructions) and interrupts are different because of the way each process is handled.
  • Page 240 Individual Instruction Descriptions 4.14.58 RFLAG Reset Memory Flag Syntax [label] name RFLAG {flagadrs} Execution memory flag bit at {flagadrs} data memory location PC + 1 Flags Affected None Opcode Instructions RFLAG {flagadrs} Description Reset flag at addressed memory location to 0.{flagadrs} includes two groups of memory flag addresses: global flags, which are the first 64 word locations in RAM;...
  • Page 241 4.14.59 RFM Reset Fractional Mode Syntax [label] name Execution STAT.FM PC + 1 Flags Affected None Opcode Instructions Description Resets fractional mode. Clears bit 3 in status register (STAT). Disable multiplier shift mode for unsigned fractional or integer arithmetic. See Also Example 4.14.59.1 Resets the fractional mode.
  • Page 242 Individual Instruction Descriptions 4.14.60 ROVM Reset Overflow Mode Syntax [label] name ROVM Execution STAT.OM PC + 1 Flags Affected None Opcode Instructions Description Resets overflow mode in status register bit 2 (the OM bit). Disable ALU saturation output (normal mode). See Also SOVM Example 4.14.60.1...
  • Page 243 4.14.61 RPT Repeat Next Instruction Syntax [label] name {adrs} imm8 Execution IF RPT {adrs} load src to repeat counter. ELSE load imm8 to repeat counter. (mask interrupt) repeat next instruction (repeat counter value + 2) times. PC + w (next instruction)+1 Flags Affected None Opcode...
  • Page 244 Individual Instruction Descriptions 4.14.62 RTAG Reset Tag Syntax [label] name dest RTAG {adrs} Execution memory tag bit at {adrs} data memory location PC + 1 Flags Affected None Opcode Instructions RTAG {adrs} Description Resets tag bit at addressed memory location. All addressing modes are available.
  • Page 245 4.14.63 RXM Reset Extended Sign Mode Syntax [label] name Execution STAT.XM PC + 1 Flags Affected None Opcode Instructions Description Reset extended sign mode status register bit 0 (the XM bit) to 0. See Also Example 4.14.63.1 Resets the sign extension mode to normal mode. Sets XM bit of STAT to 0. Individual Instruction Descriptions Clock, clk Word, w...
  • Page 246 Individual Instruction Descriptions 4.14.64 SFLAG Set Memory Flag Syntax [label] name dest SFLAG {flagadrs} Execution memory flag bit at {flagadrs} data memory location PC + 1 Flags Affected None Opcode Instructions SFLAG {flagadrs} Description Set flag at addressed memory location. {flagadrs} includes two groups of memory flag adrresses: global flags, which are the first 64 words in RAM;...
  • Page 247 4.14.65 SFM Set Fractional Mode Syntax [label] name Execution STAT.FM PC + 1 Flags Affected None Opcode Instructions Description Sets bit 3 (the FM bit) in status register (STAT) to 1. Enable multiplier shift mode for signed fractional arithmetic. Example 4.14.65.1 Set fractional mode.

  • Page 248: Shift Left

    Individual Instruction Descriptions 4.14.66 SHL Shift Left Syntax [label] name dest [, mod] An[~] [, next A] Execution [premodify AP if mod specified] PH, PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHL An[~] [, next A] Description Premodify the accumulator pointer if specified.
  • Page 249 4.14.67 SHLAC Shift Left Accumulator Syntax [label] name dest, src [, mod] SHLAC An[~], An[~] [, next A] Execution [premodify AP if mod specified] dest src << 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHLAC An[~], An[~] [, next A]...
  • Page 250 Individual Instruction Descriptions 4.14.68 SHLACS Shift Left Accumulator String Individually Syntax [label] name dest, src SHLACS An[~], An[~] Execution dest src << 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHLACS An[~], An[~] Description Shift the source accumulator string src (or its offset) left one bit and store the result in destination accumulator string (or its offset).
  • Page 251 4.14.69 SHLAPL Shift Left with Accumulate Syntax [label] name dest, src SHLAPL An, {adrs} SHLAPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH, PL src << SV dest dest + PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode...
  • Page 252 Individual Instruction Descriptions 4.14.70 SHLAPLS Shift Left String With Accumulate Syntax [label] name dest, src SHLAPLS An, {adrs} SHLAPLS An[~], An[~] Execution PH, PL src << SV dest dest + PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode Instructions...
  • Page 253 4.14.71 SHLS Shift Left Accumulator String to Product Syntax [label] name dest SHLS An[~] Execution PH, PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHLS An[~] Description Shift accumulator string value left n a ((n + 2) x 16) -bit result.
  • Page 254 Individual Instruction Descriptions 4.14.72 SHLSPL Shift Left With Subtract PL Syntax [label] name dest, src SHLSPL An, {adrs} SHLSPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH, PL src << SV dest dest – PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}:...
  • Page 255 4.14.73 SHLSPLS Shift Left String With Subtract PL Syntax [label] name dest, src SHLSPLS An, {adrs} SHLSPLS An[~], An[~] Execution PH, PL src << SV dest dest – PL PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode Instructions...
  • Page 256 Individual Instruction Descriptions 4.14.74 SHLTPL Shift Left and Transfer PL to Accumulator Syntax [label] name dest, src SHLTPL An, {adrs} SHLTPL An[~], An[~] [, next A] Execution [premodify AP if mod specified] PH, PL src << SV dest PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}:...
  • Page 257 4.14.75 SHLTPLS Shift Left String and Transfer PL to Accumulator Syntax [label] name dest, src SHLTPLS An, {adrs} SHLTPLS An[~], An[~] Execution PH, PL src << SV dest PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly src is {adrs}: Opcode Instructions...
  • Page 258 Individual Instruction Descriptions 4.14.76 SHRAC Shift Accumulator Right Syntax [label] name dest, src, [, mod] SHRAC An[~], An[~] [, next A] Execution [premodify AP if mod specified] dest src >> 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHRAC An[~], An[~] [, next a]...
  • Page 259 4.14.77 SHRACS Shift Accumulator String Right Syntax [label] name dest, src SHRACS An[~], An[~] Execution dest src >> 1 PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions SHRACS An[~], An[~] Description Shift accumulator string right one bit and store the result into An[~] string. MSB of each accumulator in the result will be set according to extended sign mode (XM) bit in the status register.
  • Page 260 Individual Instruction Descriptions 4.14.78 SOVM Set Overflow Mode Syntax [label] name SOVM Execution STAT.OM PC + 1 Flags Affected None Opcode Instructions SOVM Description Sets overflow mode in status register (STAT) bit 2 to 1. Enable ALU saturation output (DSP mode). See Also ROVM Example 4.14.78.1...
  • Page 261 4.14.79 STAG Set Tag Syntax [label] name dest STAG {adrs} Execution memory tag bit at address adrs PC + w Flags Affected None Opcode Instructions STAG {adrs} Description Sets the tag bit at the addressed memory location. All addressing modes are available.
  • Page 262 Individual Instruction Descriptions 4.14.80 SUB Subtract Syntax [label] name dest, src, src1, [next A]] An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An, An~ [, next A] An[~], An~, An [, next A] Rx, imm16 Rx, R5 Execution...
  • Page 263 Syntax Description SUB An[~], An, {adrs} [, next A] Subtract effective data memory word from An[~], store result in An SUB An[~], An[~], imm16 [, next A] Subtract immediate word from An[~], store result in An[~] SUB An[~], An[~], PH [, next A] Subtract Product High (PH) register from An[~], store result in An[~] SUB An[~], An, An~ [, next A] Subtract An~ word from An word, store result in An[~]...
  • Page 264 Individual Instruction Descriptions 4.14.81 SUBB Subtract Byte Syntax [label] name dest, src SUBB An, imm8 SUBB Rx, imm8 Execution dest dest – imm8 PC + 1 Flags Affected dest is An: dest is Rx: Opcode Instructions SUBB An imm8 SUBB Rx, imm8 Description Subtract value of src byte from value of dest byte and store result in dest.
  • Page 265 4.14.82 SUBS Subtract Accumulataor String Syntax [label] name dest, src, src1 SUBS An[~], An, {adrs} SUBS An[~], An[~], pma16 SUBS An[~], An, An~ SUBS An[~], An~, An † SUBS An[~], An[~], PH † This instruction ignores the string count, executing only once but maintains the CF and ZF status of the previous multi- ply or shift operation as if the sequence was a single string.
  • Page 266 Individual Instruction Descriptions Syntax Description SUBS An[~], An, {adrs} Subtract data memory string from An string, store result in An[~] string SUBS An[~], An[~], pma16 Subtract program memory string from An[~] string, store result in An[~] string SUBS An[~], An, An~ Subtract An~ string from An string, store result in An[~] string SUBS An[~], An~, An Subtract An string from An~ string, store result in An[~] string...
  • Page 267 4.14.83 SXM Set Extended Sign Mode Syntax [label] name Execution STAT.XM PC + 1 Flags Affected None Opcode Instructions Description Sets extended sign mode status register (STAT) bit 0 to 1. See Also Example 4.14.83.1 Set XM bit of STAT to 1. Now all arithematic operation will be in sign extention mode. Individual Instruction Descriptions Clock, clk Word, w...
  • Page 268 Individual Instruction Descriptions 4.14.84 VCALL Vectored Call Syntax [label] name dest VCALL vector8 Execution Push PC + 1 *(0x7F00 + vector8) R7 + 2 Flags Affected None Opcode Instructions VCALL vector8 Description Unconditional vectored call (Macro call). Push next address onto stack, load PC with the content of the address obtained by adding vector8 to 0x7F00.
  • Page 269 4.14.85 XOR Logical XOR Syntax [label] name dest, src, src1 [, mod] An, {adrs} An[~], An[~], imm16 [, next A] An[~], An~, An [, next A] TFn, {flagadrs} TFn, {cc} [, Rx] Execution [premodify AP if mod specified] dest dest XOR src dest src1 XOR src PC + w...
  • Page 270 Individual Instruction Descriptions See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS Example 4.14.85.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1. Example 4.14.85.2 XOR A0, A0, 2, ++A Pre–increment pointer AP0, then XOR immediate value 2 to new A0 and store result in A0. Example 4.14.85.3 XOR A1, A1~, A1 XOR accumulator A1 to accumulator A1~, put result in accumulator A1.
  • Page 271 4.14.86 XORB Logical XOR Byte Syntax [label] name dest, src XORB An, imm8 Execution An XOR imm8 PC + 1 Flags Affected dest is An: Opcode Instructions XORB An, imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte. Result is stored in accumulator An.
  • Page 272 Individual Instruction Descriptions 4.14.87 XORS Logical XOR String Syntax [label] name dest, src [, src1] XORS An, {adrs} XORS An[~], An[~], pma16 XORS An[~], An~, An Execution dest dest XOR src dest src1 XOR src PC + w Flags Affected dest is An: src is {adrs}: Opcode...
  • Page 273 4.14.88 ZAC Zero Accumulator Syntax [label] name dest [, mod] An[~] [, next A] Execution [premodify AP if mod specified] dest PC + 1 Flags Affected ZF = 1 Instructions ZAC An[~] [, next A] Description Zero the specified accumulator. Preincrement or predecrement accumulator pointer APn, if specified.
  • Page 274 Individual Instruction Descriptions 4.14.89 ZACS Zero Accumulator String Syntax [label] name dest Execution dest PC + 1 Flags Affected ZF = 1 Instructions ZACS An[~] Description Zero the specified accumulator string. See Also Example 4.14.89.1 ZACS A1~ Reset the content of offset accumulator string A1~ to zero. Example 4.14.89.2 MOV STR, 32–2 ZACS A0...

  • Page 275: Instruction Set Encoding

    4.15 Instruction Set Encoding Instructions ADD An[~], An, {adrs} [, next A] ADD An[~], An[~], imm16 [, next A] ADD An[~], An[~], PH [, next A] ADD An[~], An~, An [, next A] ADD Rx, imm16 ADD Rx, R5 ADD APn, imm5 ADDB An, imm5 ADDB Rx, imm8 ADDS An[~], An, {adrs}...
  • Page 276 Instruction Set Encoding Instructions CMP An, {adrs} CMP An[~], imm16 [, next A] CMP An, An~ [, next A] CMP An~, An [, next A] CMP Rx, imm16 CMP Rx, R5 CMPB An, imm8 CMPB Rx, imm8 CMPS An, {adrs} CMPS An[~], pma16 CMPS An, An~ CMPS An~, An...
  • Page 277 Instructions JMP pma16, Rx–– JMP pma16, Rx++R5 JMP *An Jcc pma16 Jcc pma16, Rx++ Jcc pma16, Rx–– Jcc pma16, Rx++R5 MOV {adrs}, An[~] [, next A] MOV An[~], {adrs} [, next A] MOV {adrs}, *An MOV An[~], imm16 [, next A] MOV MR, imm16 [, next A] MOV An, An~ [, next A] MOV An[~], PH [, next A]...
  • Page 278 Instruction Set Encoding Instructions MOV PH, {adrs} MOV MR, {adrs} MOV APn, {adrs} MOV STAT, {adrs} MOV TOS, {adrs} MOV {adrs}, PH MOV {adrs}, MR MOV {adrs}, STAT MOV {adrs}, STR MOV {adrs}, DP MOV {adrs}, SV MOV {adrs}, APn MOV {adrs}, TOS MOV STR, {adrs} MOV {flagadrs} †...
  • Page 279 Instructions MOVB {adrs}, An MOVB An, imm8 MOVB MR, imm8 MOVB Rx, imm8 MOVBS An, {adrs} MOVBS {adrs}, An MOVS An[~], {adrs} MOVS {adrs}, An[~] MOVS {adrs}, *An MOVS An[~], pma16 MOVS PH, An[~] MOVS SV, An[~] MOVS An[~], PH MOVS An, An~ MOVS MR, An[~] MOVS An[~], *An[~]...
  • Page 280 Instruction Set Encoding Instructions MUL {adrs} MULR {adrs} MULS An[~] MULAPL An, {adrs} MULAPL An[~], An[~], [next A] MULAPLS An, {adrs} MULAPLS An[~], An[~] MULSPL An, {adrs} MULSPL An[~], An[~] [, next A] MULSPLS An, {adrs} MULSPLS An[~], An[~] MULTPL An, {adrs} MULTPL An[~], An[~] [, next A] MUL TPLS An, {adrs} MULTPLS An[~], An[~]...
  • Page 281 Instructions ORS An[~], An[~], pma16 ORS An[~], An~, An OUT port4, {adrs} OUT port6, An[~] OUTS port6, An[~] RPT {adrs} RPT imm8 RFLAG {flagadrs} ROVM RTAG {adrs} SFLAG {flagadrs} SHL An[~] [, next A] SHLS An[~] SHLAPL An, {adrs} SHLAPL An[~], An[~] [, next A] SHLAPLS An, {adrs} SHLAPLS An[~], An[~] SHLSPL An, {adrs}...
  • Page 282 Instruction Set Encoding Instructions SHLTPLS An[~], An[~] SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~] SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] STAG {adrs} SOVM SUB An[~], An, {adrs} [, next A] SUB An[~], An[~], imm16 [, next A] SUB An[~], An[~], PH [, next A] SUB An[~], An, An~ [, next A] SUB An[~], An~, An [, next A]...
  • Page 283 Instructions ZAC An[~] [, next A] ZACS An[~] cc names cc name Not cc name RNZP RLZP RNLZP NTF1 NTF2 NTAG NIN1 NIN2 next A Description True condition (Not true condition) Tr e condition (N t tr e condition) Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF 0 or CF 0)

  • Page 284: Instruction Set Summary

    Instruction Set Summary 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction. name dest [, src] [, src1] [,mod] An[~], An, {adrs} [, next A]...
  • Page 285 name dest [, src] [, src1] [,mod] Rx, imm16 An[~], An[~] [, next A] An[~], imm16 [, next A] Rx, R5 CMPB An, imm8 CMPB Rx, imm8 CMPS An, {adrs} CMPS An[~], pma16 CMPS An, An~ CMPS An~, An An, *Rx CORK An, *Rx ENDLOOP...
  • Page 286 Instruction Set Summary name dest [, src] [, src1] [,mod] {adrs}, An[~] [, next A] An[~], {adrs} [, next A] {adrs}, *An An[~], imm16 [, next A] MR, imm16 [, next A] An, An~ [, next A] An[~], PH [, next A] SV, An[~] [, next A] PH, An[~] [, next A] An[~], *An[~] [, next A]...
  • Page 287 name dest [, src] [, src1] [,mod] {adrs}, SV {adrs}, APn {adrs}, TOS STR, {adrs} † {flagadrs} , TFn † TFn, {flagadrs} TFn, {cc} [, Rx] STR, imm8 APn, imm5 † MOVB An, {adrs} † MOVB {adrs} , An MOVB An, imm8 MOVB MR, imm8...
  • Page 288 Instruction Set Summary name dest [, src] [, src1] [,mod] MOVU MR, {adrs} MOVAPH An, MR, {adrs} MOVAPHS An, MR, {adrs} MOVSPH An, MR, {adrs} MOVSPHS An, MR, {adrs} An[~] [, next A] {adrs} MULR {adrs} MULS An[~] MULAPL An, {adrs} MULAPL An[~], An[~] [, next A] MULAPLS...
  • Page 289 name dest [, src] [, src1] [,mod] TFn, {flagadrs} TFn, {cc} [, Rx] An, imm8 An, {adrs} An[~], An[~], pma16 An[~], An~, An port4, {adrs} OUTS port6, An[~] {adrs} imm8 RFLAG {flagadrs} ROVM RTAG {adrs} SFLAG {flagadrs} An[~] [, next A] SHLS An[~] SHLAPL...
  • Page 290 Instruction Set Summary name dest [, src] [, src1] [,mod] SHLTPLS An, {adrs} SHLTPLS An[~], An[~] SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~] SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] STAG {adrs} SOVM An[~], An, {adrs} [, next A] An[~], An[~], imm16 [, next A] An[~], An[~], PH [, next A] An[~], An, An~ [, next A]...
  • Page 291 name dest [, src] [, src1] [,mod] XORS An, {adrs} XORS An[~], An[~], pma16 XORS An[~], An~, An An[~] [, next A] ZACS An[~] cc names cc name Not cc name Conditional on ZF=1 (Not condition ZF=0) Conditional on SF=1 (Not condition SF=0) Conditional on CF=1 (Not condition CF=0) Conditional on ZF=0 and CF=0 (Not condition ZF 0 or CF 0) Conditional on ZF=0 and CF=1 (Not condition ZF 0 or CF 1)
  • Page 292 MSP50C614 (MSP50P614) IO Port Description Address Bits Name 0x00 Port A Data (bidirectional) 0x04 Port A Control bit C = 0 0x08 Port B Data (bidi (bidirectional) 0x0C Port B Control bit C = 0 0x10 Port C Data (bidirectional) 0x14 Port C Control bit C = 0...
  • Page 293 MSP50C614 (MSP50P614) IO Port Description Address Bits Name 0x34 DAC Control Drive Mode 3x Style DAC 5x Style DAC 0x38 Interrupt General F port Pullup Control Arm bit Arm bit Comparator 0=disable 1=enable PDM clock 0x39 Interrupt Flag Flag Register Register F port falling edge interrupt flag 0x3A...
  • Page 294 Interrupt Vector Source Trigger Event INT0 0x7FF0 DAC Timer timer underflow INT1 0x7FF1 TIMER1 timer underflow INT2 0x7FF2 TIMER2 timer underflow INT3 0x7FF3 port PD2 rising edge INT4 0x7FF4 port PD3 falling edge INT5 0x7FF5 all port F any falling edge INT6 †...
  • Page 295 10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) ClkSpdCtrl ClkSpdCtrl IntGenCtrl IntGenCtrl PLLM PLLM PDMCD Over-Sampling Register Precision Factor Value 8 bits 0x 13 0x 26 0x 4D 0x 9B 0x 26 0x 4D 0x 9B 9 bits 0x 26 0x 4D 0x 9B 0x 4D...
  • Page 296 Instruction Set Summay 4-210 Assembly Language Instructions...

  • Page 297: Code Development Tools

    Code Development Tools This chapter describes the code development tools for the MSP50C6xx family of devices. The MSP50C6xx code development tool is used to compile, assemble, link, and debug programs. A reduced function C compiler, (called C––) is also part of the code development tool.

  • Page 298: Introduction

    Introduction 5.1 Introduction The MSP50C6xx code development tool is a system made up of a personal computer (PC), the EMUC6xx software, an MSP scanport interface, and a MSP50P614 connected to the application circuits. EMUC6xx is the software that executes on the PC and provides a user interface to the compiler, assembler, linker, debugger, and MSP50P614 programmer.

  • Page 299: Pin Idc Connector (Top View Looking At The Board)

    PINOUT DETAILS It is also recommended that all production boards provide a method for connecting the MSP50C6xx code development tool to the scanport. This allows the development tool to facilitate any post-production debugging. There are several options for providing access to the scanport. If the production board has enough room, layout the footprint of the recommended connector and connect it to the scanport.

  • Page 300: Categories Of Msp50Cxx Development Tools

    I/O pins. These boards are discussed more in Sections 5.2.2 and 5.2.4. 5.2 MSP50C6xx Development Tools Guidelines This is a summary of the tools needed for code development and speech edit- ing for the MSP50C6xx family of speech processors (MSP50C614, MSP50C605, MSP50C601, and MSP50C604). 5.2.1...

  • Page 301: Tools Definitions

    ‡ Speech-EVM and EVA50C605 have similar functionality. They both function as basic target boards that support code development. For more information about these boards refer to Section 5.2.2. 5.2.1.2 Speech Editing Tools For editing and analyzing speech for the MSP50C6xx family the following is needed: Hardware Software 5.2.2...
  • Page 302 MSP50C614, MSP50C605, MSP50C601, and MSP50C604 (being used in master mode). A MSP50P614 is used on this board to emulate the MSP50C6xx core. An EPROM is used on the SPEECH-EVM board to emulate the data ROM of the MSP50C601 and the MSP50C605.
  • Page 303 Software Tools Definitions MSP50C6xx code development software (EMUC6xx) The PC based software is used for MSP50C6xx code development and requires Microsoft Windows 95 or 98 operating systems. It is one part of the MSP50C6xx code development tools, along with the MSP scanport interface, and the MSP50C6xx device on an application board.

  • Page 304: Msp50C6Xx Code Development Tools

    MSP50C614: MSP50C605: MSP50C601: MSP50C604: Applications Notes Documents that help users in developing code for MSP50C6xx devices are available. SDS6000 Speech Editing Tool manual Schematics Reference designs/schematics for the daughter cards. Schematics of the SPEECH–EVM and the EVA50C605 are also available.

  • Page 305: Hardware Tools Setup

    Step 6: Place a MSP50P614 device on the personality card that you use in Step 1. Step 7: Apply power to SPEECH-EVM (see the following note) or EVA50C605. The green light on the scanport interface should be MSP50C6xx Development Tools Guidelines Code Development Tools...

  • Page 306: Hardware Tools Setup

    MSP50C6xx Development Tools Guidelines Note: There is a three-way switch at the edge of the SPEECH-EVM board. After you apply power to the SPEECH-EVM, you have to turn on the SPEECH- EVM. There are two ways to turn on the board depending on the power...

  • Page 307: Assembler Directives

    5.4 Assembler 5.4.1 Assembler Directives Assembler directives are texts which have special meaning to the assembler. Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the assembler to initialize variables with values, assigning symbols to memory locations, assigning origin of a program, etc.
  • Page 308 Assembler (~ indicates bitwise complement) symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some ex- pression.
  • Page 309 #IF expression: The start of a conditional assembly structure expression is an arithmetic expression that can contain symbols. Caution: since conditional assembly is resolved during the first pass of the assembler, no forward referenced symbols should be used in a conditional assembly expression.
  • Page 310 CHIP_TYPE chip_name: This directive is provided for compatibility with future chips in the same family. It defines chip parameters (such as RAM and ROM size) for the assembler. For now, the only defined chip name is MSP50C6xx. DATA expression[,expression]: Introduces one or more data items, of WORD size (16 bits) .
  • Page 311 END expression: Expression defines the start vector for the current assembly program. This directive generates the following assembly code; AORG 0xFFFF DATA expression which defines the start vector of the program, i.e., the program address where execution begins when the chip is installed. label EQU expression: Associates the value of expression with label.

  • Page 312: C– – Compiler

    C– – files (extension .cmm) and assembly language files (extension .asm). 5.5.1 Foreword C–– is a high level language to be used with the MSP50C6xx microprocessors. Although it looks a lot like C, it has some limitations/restrictions which will be highlighted throughout the remainder of this chapter.

  • Page 313: External References

    16 bit integers, whereas an integer string of length n represents a single integer with 16*n bits. In C– –, MSP50C6xx strings are declared as arrays of integers, but must be operated upon using the special purpose string arithmetic functions described below.

  • Page 314: C– – Directives

    C– – Compiler 5.5.4 C– – Directives C– – has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler. 5.5.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement string for a given string Example:...

  • Page 315: Include Files

    Example: #include “file.h” #include <stdio.h> The include directories are defined on the cmm_input structure passed to the compiler. There is no limit to the nesting of include files. 5.5.4.4 #asm All text following this directive is inserted as is in the output file, and is considered as assembly language (hence not compiled).
  • Page 316 C– – Compiler /********************************/ /* Prototypes for C– –functions */ /********************************/ cmm_func add_string(int *result,int *str1,int *str2,int lg); cmm_func sub_string(int *result,int *str1,int *str2,int lg); cmm_func mul_string(int *result,int *str1,int mult,int lg1,int lgr); cmm_func umul_string(int *result,int *str1,unsigned int mult,int lg1,int lgr); cmm_func or_string(int *result,int *str1,int *str2,int lg); cmm_func and_string(int *result,int *str1,int *str2,int lg);...

  • Page 317: Function Prototypes And Declarations

    C– –program: #define cmm_func A library of regular C functions to substitute for the special MSP50C6xx functions is supplied with the C– – compiler, allowing the user to compare the results of regular C programs with those of C– –programs. The library is contained in the C source file cmm_func.c .It should be linked with the C...

  • Page 318: String Functions

    UGES_N >= ? (unsigned) UGTS_N > ? (unsigned) A major feature of the MSP50C6xx is that the string length present in the string register is the actual length of the string minus two. To avoid confusion, a macro is supplied that automatically translates the real length of the string to...

  • Page 319: Constant Functions

    C– – Compiler the MSP50C6xx length of the string. It is included in the cmm_macr.h file, and is called STR_LENGTH(lstr). For example, STR_LENGTH(8) is 8–2 = 6. Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string.

  • Page 320: Implementation Details

    Implementation Details 5.6 Implementation Details This section is C– – specific. 5.6.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~. CMP A0,A0~ : A0 contains a, A0~ contains b FFFF FFFF FFFF...
  • Page 321 Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a < b _ule a <= b _uge a >= b _ugt a > b The small number of comparisons was an invitation to use them as vector calls.
  • Page 322 Implementation Details 5.6.2 Division Integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We return the quotient in A0~, and the remainder in A0. We make use of A3~ and A3 for scratch pads.

  • Page 323: Programming Example

    For example: cmm_func bidon(int i1,char *i2) is valid, but: cmm_func bidon(i1,i2) int i1,char *i2; is invalid. Note: The exact implementation of the MSP50C6xx stack is as follows: on CALL: 1) Increment R7 2) Transfer TOS (top of stack) register to *R7...
  • Page 324 Implementation Details #include “cmm_macr.h” constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multiplies string m1 of length lgm1+2 by string m2 of length lgm2+2, and puts the result into string p, of length lgp+2 */ int sign,i,j;...
  • Page 325 add_string(p,pp,p,lgm1+i+1); if(sign == –1) neg_string(pp,p,STR_LENGTH((lgp+2))); copy_string(p,pp,STR_LENGTH((lgp+2))); free(mm1); free(mm2); free(pp); cmm_func main(int argc,char *argv) int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); 5.6.5 Programming Example, C –– With Assembly Routines There are several important considerations when using the C– – compiler. The ram allocation must be coordinated so that a location isn’t accidentally used twice.
  • Page 326 Implementation Details Here the sub files are inter_ram.irx and asm_ram.irx. The allocation for in- ter_ram.irx begins at memory location 2. This is because the memory location 0 is reserved for use by the C– – compiler. The allocation for asm_ram.irx be- gins where the allocation ended for inter_ram.irx.
  • Page 327 |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |R7|Param 1 |–––––––––––––––| |–––––––––––––––| |Param 1 |–––––––––––––––| |–––––––––––––––| R7,R5 |Stack data |R5|Stack data |–––––––––––––––| |–––––––––––––––| Before call Parameter 1 Implementation Details |–––––––––––––––| |–––––––––––––––| |–––––––––––––––| |–––––––––––––––|...
  • Page 328 Implementation Details |––––––––––––––| |R7 | |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| R7 |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| R5 |Stack data |R5 |Stack data |––––––––––––––| Function call 5-32 |––––––––––––––| |––––––––––––––| |R5,R7 | |––––––––––––––| |––––––––––––––|...
  • Page 329 C to C function return (in ronco_return). |––––––––––––––| |––––––––––––––| R5 | |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| R7 |(old)R5 |(old)R5 |––––––––––––––| |––––––––––––––| |(old)R5 |(old)R5 |––––––––––––––| |––––––––––––––| |Return Addr |R7 |Return Addr |––––––––––––––| |––––––––––––––| |Return Addr |Return Addr |––––––––––––––| |––––––––––––––| |Param 2 |Param 2 |––––––––––––––| |––––––––––––––| |Param 2...
  • Page 330 Implementation Details |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |(old)R5 |––––––––––––––| |(old)R5 |––––––––––––––| |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| R7,R5 |Stack data |––––––––––––––| SUBB R7,4 5-34...
  • Page 331 C to ASM function call. The stack is shown after the operation on the bottom is performed. |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |R7 |Param 1 |––––––––––––––| |––––––––––––––| |Param 1 |––––––––––––––| |––––––––––––––|...
  • Page 332 Implementation Details |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| |Stack data |––––––––––––––| Function call 5-36...
  • Page 333 C to ASM function return |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |––––––––––––––| |Return Addr |––––––––––––––| |Return Addr |––––––––––––––| |Param 2 |––––––––––––––| |Param 2 |––––––––––––––| |Param 1 |––––––––––––––| |Param 1 |––––––––––––––| |Stack data |––––––––––––––| 5.7 C–– Efficiency C–– allows top-level control code to be written in a C-like language. It does have limitations though.
  • Page 334 C– – Efficiency repetition), but for loops are implemented with much greater overhead (one conditional jump and three unconditional jumps per repetition.) For this reason, it is best to replace for loops with while loops. (This was not done in the example projects for the sake of readability and to provide an example of a C–...
  • Page 335 5.7.1 Real Time Clock Example The C– – clock works as follows. The Timer2 ISR is set to fire at 1-second intervals. Inside the ISR a counter is incremented by one each time it fires. An assembly routine in cmm1.asm (_getSecondsPassed) disables the interrupts, retrieves the counter, resets it, and turns the interrupts back on.
  • Page 336 Allocates RAM for ISRs and mainasm.asm vroncof2.asm Assembly routines for built in C– – functions and ISR vector table rtc.rpj Project file generated by MSP50C6xx development tool [modules] Directory for ISRs, general purpose files, and plugable modules [general] Directory holding general-purpose files for initialization and mnemonics init.asm...
  • Page 337 Seven of the files are important to the functionality of this project. The Timer2 ISR (tim2_isr.asm) forms the basis for the RTC so it will be discussed first. timer2_isr mov *save_tim2_stat,STAT *save_tim2_a0,a0 ; timer fired so 1 second passed ; update the variable storing the seconds passed so far mov a0, *seconds_passed add a0, a0, 1 mov *seconds_passed, a0...
  • Page 338 C– – Efficiency change is the table of interrupt vectors. At the top of the file is a list of interrupt labels. The ones that are not used are commented out with a semicolon. external DAC_ISR external timer1_isr external timer2_isr external external external...
  • Page 339 Mainasm.asm contains the most complex assembly. It is responsible for initializing assembly variables, enabling or disabling interrupts, and setting up any timers or I/O ports. It also enables the interrupts. The part that is important to the project, _goasm, is called at the beginning of the C– – main routine. ;**************************************************************** ;...
  • Page 340 C– – Efficiency mov *seconds_passed, a0 inte mov a0, a0~ The file only has one C– – callable function, getSecondsPassed. The function reads the value in seconds_passed and returns it in A0. All C– – functions have an underscore preceding their name in assembly. The underscore is ignored when programming in C–...
  • Page 341 ; MAIN.CMM ; Revision 1.00 ****************************************************************/ #include ”ram\ram.h” cmm_func goasm(); // an pseudo main asm routine cmm_func getSecondsPassed(); // Retrieves the counter maintained // by the Timer2 ISR and resets the // counter. int days=0; int hours=12; int minutes=0; seconds=0; int ampm=0;...
  • Page 342 C– – Efficiency assembly divided by two because C– – integers are 16 bit. The perl script in the main project directory can be used to resize bogus automatically or it can be done manually. To use the perl script, build the project after making any changes to assembly ram allocation.
  • Page 343 [Root] cmm1.asm cmm1_ram.irx flags.irx main.cmm main.irx main_ram.irx mainasm.asm vroncof2.asm rtc.rpj [dsp] [celp] celp.irx celp4.obj [common] util.obj util2.obj [general] dsp_var.irx dsputil.asm getbits.asm speak.asm speak.irx spk_ram.irx [melp] melp.irx melp.obj [modules] [general] init.asm io_ports.irx sleep.asm [isr] tim2_isr.asm dac_isr.asm tim1_isr.asm [speech] [celp] ampm.qfm days.qfm ones.qfm teens.qfm C–...
  • Page 344 C– – Efficiency [ram] Descriptions of files that are also in Project 1 have been omitted. [dsp] Directory holding files for speech synthesis. [celp] celp.irx celp4.obj [common] util.obj util2.obj [general] dsp_var.irx dsputil.asm getbits.asm speak.asm speak.irx speak_ram.irx [melp] melp.irx melp.obj sleep.asm dac_isr.asm tim1_isr.asm [speech]...
  • Page 345 In main_ram.irx, two variables were added to save and restore r3 and r5 when speaking. These registers are used by C– – so it is a good idea to save and restore them in case they are modified by the speech routines. This is a good example of adding RAM for use by cmm1.asm.
  • Page 346 C– – Efficiency inte iret Cmm1.asm was modified to include routines for sleeping and speaking from C––. global _inportD global _getSecondsPassed global _sleepQuarterSec global _speakDays global _speakOnes global _speakTens global _speakTeens global _speakAMPM New C– – callable functions were declared global. external sleep_light external...
  • Page 347 DATA MON ;0 DATA TUE ;1 DATA WED ;2 DATA THU ;3 DATA FRI ;4 DATA SAT ;5 DATA SUN ;6 C–– callable speech routines, like the above for speaking days were added. An integer phrase number is passed on the stack. The routines get this value from the stack and do a table lookup to get the address of the correct phrase.
  • Page 348 C– – Efficiency playing. In some cases speech files can be played to debounce keys. This is why there is no delay in the main() function. Pressing SW2 calls a function, but the switch will not be read again until the time has been spoken so there is no need for a delay there.
  • Page 349 melp.irx melp.obj [modules] [general] init.asm io_ports.irx sleep.asm [isr] tim2_isr.asm dac_isr.asm tim1_isr.asm [lcd] lcd.asm lcd.irx lcd_ram.irx [speech] [celp] ampm.qfm days.qfm ones.qfm teens.qfm tens.qfm [melp] ampm.qfm days.qfm ones.qfm teens.qfm tens.qfm [ram] ram.h ram.irx C– – Efficiency Code Development Tools 5-53...
  • Page 350 C– – Efficiency Descriptions of files that are also in Project 2 have been omitted. [lcd] lcd.asm lcd.irx lcd_ram.irx The only changes to the assembly are in mainasm.asm and in cmm1.asm. In mainasm.asm, two calls are made to setup and initialize the lcd. To allow this, the labels for the routines were declared external.
  • Page 351 writeCharacter(’:’); writeNum(time[WIDTH*0+2]); //seconds writeCharacter(’ ’); if(time[WIDTH*1+1]==0){ //ampm writeCharacter(’A’); else{ writeCharacter(’P’); writeCharacter(’M’); writeCharacter(’ ’); switch(time[WIDTH*1+0]){ //days case 0: writeCharacter(’M’); writeCharacter(’O’); writeCharacter(’N’); break; case 1: writeCharacter(’T’); writeCharacter(’U’); writeCharacter(’E’); break; case 2: writeCharacter(’W’); writeCharacter(’E’); writeCharacter(’D’); break; case 3: writeCharacter(’T’); writeCharacter(’H’); writeCharacter(’U’); break; case 4: writeCharacter(’F’);...
  • Page 352 C– – Efficiency writeCharacter(’ ’); break; case 1: writeCharacter(’ ’); writeCharacter(’(’); rowOne(); for(temp=0; temp<17; temp++) writeCharacter(’ ’); writeCharacter(’o’); break; case 2: writeCharacter(’ ’); writeCharacter(’|’); rowOne(); for(temp=0; temp<16; temp++) writeCharacter(’ ’); writeCharacter(’o’); writeCharacter(’ ’); break; case 3: writeCharacter(’ ’); writeCharacter(’)’); rowOne(); for(temp=0;...

  • Page 353: Beware Of Stack Corruption

    5.8 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get corrupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *A0 This code will work perfectly well if no interrupts happen before SUBB and MOV instruction.

  • Page 354: Reported Bugs With Code Development Tool

    Reported Bugs With Code Development Tool 5.9 Reported Bugs With Code Development Tool The following are reported bugs for code development tool version 2.39. Breakpoint: Placement of hardware breakpoints is important for reliable operation. Pipeline latency and sleep modes affect the scan logic and prevent hardware breakpoints from working in the following cases.
  • Page 355 ......... . . Initializing the MSP50C6xx .

  • Page 356: Application Circuits

    Application Circuits 6.1 Application Circuits Figure 6–1. Minimum Circuit Configuration for the C614/P614 Using a Resistor-Trimmed Oscillator 0.1 F 470 k REFERENCE (1%) 3300 pF † The diode across V DD and V PP may be omitted (shorted), if the application does not require use of the scan port interface. The same applies for the 1-k resistor which appears at the RESET pin;...

  • Page 357: Minimum Circuit Configuration For The C614/P614 Using A Crystal-Referenced Oscillator

    It is of particular importance to provide a separate decoupling capacitor for the pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. An alternate circuit, for better clock-precision and better battery life, includes a crystal oscillator.

  • Page 358: Initializing The Msp50C6Xx

    OSC (22 pF, 10 M , 32 kHz). 6.2 Initializing the MSP50C6xx The initialization code for the MSP50C6xx is in the file INIT.ASM, in the MODULES\GENERAL directory of the TI-TALKS code (see the following information).

  • Page 359: File Init.asm

    – 2 BEGLOOP rtag ;reset tag mov *r0++,a0 ;clear the RAM ENDLOOP mov STR,0 ;clear string register to distinguish between P and C parts. Top 5 bits go to bits !!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!! ;do a loop RAM_SIZE times Initializing the MSP50C6xx Applications...
  • Page 360 Initializing the MSP50C6xx mov ap0,0 ;clear accum pointer 0 mov ap1,0 ;clear accum pointer 1 mov ap2,0 ;clear accum pointer 2 mov ap3,0 ;clear accum pointer 3 mov r0,0 ;clear register 0 mov r1,0 ;clear register 1 mov r2,0 ;clear register 2 mov r3,0 ;clear register 3...
  • Page 361 ;save the ClkSpdCtrl value for later, when ;disable TIMER 2 ;use 32 kHz crystal as source, wake up from TIM2 ;turn off TIMER 2 ––– added 28.11.99 For C5x style set bit 3 ;choose 10 bit DAC, C3x style Initializing the MSP50C6xx Applications...

  • Page 362: Ti-Talks Example Code

    (the red LED and the green LED on the scan port are both illuminated) before attempting to start the code development tool. Click on Start, go to Programs – EMUC6xx and click on MSP50C6xx Code Development icon. To open a project click on Project – New Project and select the desired project file.

  • Page 363: Ram Overlay

    Note that TI-TALKS604 indicates version 604 of TI-TALKS code. 6.4 RAM Overlay The RAM map for the MSP50C6xx family is quite complex. Here the method of overlaying the RAM is explained, together with examples of how to add variables for customer code.
  • Page 364 RAM Overlay 6.4.2 RAM Overlay RAM is reserved for variables in the following way. The start address of the variable is equal to the address of the previous variable, plus the size of that variable. The size of VAR1 thus depends on the start address of the next variable.

  • Page 365: Common Problems

    save_tim2_stat save_tim1_a0a + 2 * 1 save_tim2_a0 save_tim2_stat + 2 * 1 save_tim2_a0a save_tim2_a0 + 2 * 1 ;End of RAM RAMEND_CUSTOMER save_tim2_a0a RAMLENGTH_CUSTOMER RAMEND_CUSTOMER – RAMSTART_CUSTOMER After adding new_var the MAIN_RAM.IRX file would look like this: ;**************************************************************** ; MAIN_RAM.IRX ;...
  • Page 366 6-12...

  • Page 367: Customer Information

    Customer Information Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter. Topic Mechanical Information ........Customer Information Fields in the ROM Speech Development Cycle .

  • Page 368: Mechanical Information

    120-pin, PGA-windowed ceramic package. NOTE: Scan Port Bond Out The scan port interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx code development tools. The SCANIN, SCANOUT, SCANCLK, SYNC, and TEST pins are dedicated to the scan port interface.

  • Page 369: Signal And Pad Descriptions For The Msp50C614

    Refer to Section 3.3, Comparator, for details. SCANIN SCANOUT SCANCLK SYNC TEST The scan port pins must be bonded out on any MSP50C6xx production board. Consult the “Important Note regarding Scan Port Bond Out”. OSCOUT OSCIN Digital-to-Analog Sound Outputs DACP...

  • Page 370: Signal And Pad Descriptions For The Msp50C605

    Mechanical Information Table 7–2. Signal and Pad Descriptions for the MSP50C605 SIGNAL PIN NUMBER PAD NUMBER PC0 – PC7 89 – 82 PD0 – PD7 99 – 92 PE0 – PE7 46 – 39 PF0 – PF7 16 – 9 Pins PD 4 and PD 5 may be dedicated to the comparator function, if the comparator enable bit is set.

  • Page 371: Signal And Pad Descriptions For The Msp50C601

    Table 7–3. Signal and Pad Descriptions for the MSP50C601 SIGNAL PIN NUMBER PAD NUMBER PC0 – PC7 89 – 82 PD0 – PD7 99 – 92 PE0 – PE7 46 – 39 PF0 – PF7 16 – 9 Pins PD 4 and PD 5 may be dedicated to the comparator function, if the comparator enable bit is set. Refer to Section 3.3, Comparator, for details.

  • Page 372: Signal And Pad Descriptions For The Msp50C604

    Mechanical Information Table 7–4. Signal and Pad Descriptions for the MSP50C604 SIGNAL PIN NUMBER PAD NUMBER PC0 – PC7 89 – 82 PD0 – PD7 99 – 92 PE0 – PE7 46 – 39 PF0 – PF7 16 – 9 Pins PD 4 and PD 5 may be dedicated to the comparator function, if the comparator enable bit is set.

  • Page 373: Pin Qfp Mechanical Information

    Figure 7–1. 100-Pin QFP Mechanical Information 0,65 18,85 TYP 2,90 2,50 3,40 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 0,38 0,13 0,22 12,35 TYP 20,20 19,80 23,45...

  • Page 374: Pin Qfp Mechanical Information

    Mechanical Information Figure 7–2. 64-Pin QFP Mechanical Information 0,50 7,50 TYP 10,20 9,80 12,20 11,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D.

  • Page 375: Pin, Grid Array Package For The Development Device, Msp50P614

    The MSP50C614 is available in a windowed-ceramic, 120-pin, grid array (PGA) packaged for use in software development and prototyping. This PGA package is shown in Figure 7–3. Figure 7–3. 120-Pin, Grid Array Package for the Development Device, MSP50P614 10 9 8 7 6 5 4 3 2 1 (TOP VIEW) Note: The PGA package is only available in limited quantities for development...

  • Page 376: Bottom View Of 120-Pin Pga Package Of The Msp50P614

    Mechanical Information Figure 7–4. Bottom View of 120-Pin PGA Package of the MSP50P614 † V DD PF 7 PF 5 DAC P PF 6 † V SS PD 0 V DD PD 3 PD 1 PD 5 PD 4 PD 2 V DD PD 7 PD 6...

  • Page 377: Customer Information Fields In The Rom

    7.2 Customer Information Fields in the ROM Customer code information is inserted in the ROM by Texas Instruments. This information appears as seven distinct fields within the ROM test-area. The ROM test-area extends from address 0x0000 to 0x07FF. The code-release information is stored in locations 0x0006 through 0x000C.

  • Page 378: Device Production Sequence

    Speech Development Cycle 7.3 Speech Development Cycle A sample speech development cycle is shown in Figure 7–5. Some of the components, such as speech recording, speech analysis, speech editing, and speech evaluation, require different hardware and software. TI provides a speech development tool, called the SDS6000, which allows the user to perform speech analysis using various algorithms, speech editing for certain algorithms, and to evaluate synthesis results through playback of encoded...
  • Page 379 † For MSP50C601 and MSP50C605 devices, the customer needs to send the code in QBN format and speech data in BIN format. ‡ For MSP50C601 and MSP50C605 devices, Texas Instruments will send the verification code in QBN format and the verification speech data in BIN format.

  • Page 380: New Product Release Forms (Nprf)

    Ordering Information 7.5 Ordering Information Because the MSP50C6xx are custom devices, they receive a distinct identifi- cation, as follows: Gate Code Family CSM: Custom Member Synthesizer (614, 605, etc.) With Memory 7.6 New Product Release Forms (NPRF) The new product release form is used to track and document all the steps involved in implementing a new speech code onto one of the parent speech devices.
  • Page 381 NEW PRODUCT RELEASE FORM FOR MSP50C614 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi- croprocessor code and speech data. Company:_________________ Project Name:_________________ Purchase Order #:______________ Management Contact:_________________ Technical Contact:_________________ Customer Part Number:_________________ Customer Code Version and Revision: __.__ (of format vv.rr)
  • Page 382 I authorize TI to start normal production in accordance with purchase order #______________________. By:__________________________________ Date:_____________________ ******************************************************************************** Return to: Texas Instruments, Inc. Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266–0199 OR Fax to: (214)480–7301...
  • Page 383 NEW PRODUCT RELEASE FORM FOR MSP50C604 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi- croprocessor code and speech data. Company:_________________ Project Name:_________________ Purchase Order #:______________ Management Contact:_________________ Technical Contact:_________________ Customer Part Number:_________________ Customer Code Version and Revision: __.__ (of format vv.rr)
  • Page 384 I authorize TI to start normal production in accordance with purchase order #______________________. By:__________________________________ Date:_____________________ ********************************************************************** Return to: Texas Instruments, Inc. Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266–0199 OR Fax to: (214)480–7301...
  • Page 385 NEW PRODUCT RELEASE FORM FOR MSP50C605 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi- croprocessor code and speech data. Company:_________________ Project Name:_________________ Purchase Order #:______________ Management Contact:_________________ Technical Contact:_________________ Customer Part Number:_________________ Customer Code Version and Revision: __.__ (of format vv.rr)
  • Page 386 I authorize TI to start normal production in accordance with purchase order #______________________. By:__________________________________ Date:_____________________ ********************************************************************** Return to: Texas Instruments, Inc. Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266–0199 OR Fax to: (214)480–7301...
  • Page 387 NEW PRODUCT RELEASE FORM FOR MSP50C601 SECTION 1. OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi- croprocessor code and speech data. Company:_________________ Project Name:_________________ Purchase Order #:______________ Management Contact:_________________ Technical Contact:_________________ Customer Part Number:_________________ Customer Code Version and Revision: __.__ (of format vv.rr)
  • Page 388 I authorize TI to start normal production in accordance with purchase order #______________________. By:__________________________________ Date:_____________________ ********************************************************************** Return to: Texas Instruments, Inc. Attn: Code Release Team P.O. Box 660199, M/S 8718 Dallas, TX 75266–0199 OR Fax to: (214)480–7301...

  • Page 389: Additional Information

    Appendix A Appendix A Additional Information This appendix contains additional information for the MSP50C6xx mixed-sig- nal processor. Topic Page Additional Information ........
  • Page 390 Additional Information A.1 Additional Information For current information regarding the MSP50C6xx devices (data sheets, de- velopment tools, etc.), visit the TI Speech Web site: http://www.ti.com/sc/speech...

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