Texas Instruments TMS3320C5515 User Manual
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Texas Instruments TMS3320C5515 User Manual

Texas Instruments TMS3320C5515 User Manual

Dsp system - digital signal processor
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TMS3320C5515 DSP System
User's Guide
Literature Number: SPRUFX5A
October 2010 – Revised November 2010

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Summary of Contents for Texas Instruments TMS3320C5515

  • Page 1 TMS3320C5515 DSP System User's Guide Literature Number: SPRUFX5A October 2010 – Revised November 2010...
  • Page 2 SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    Device Configuration 1.7.4 DMA Controller Configuration 1.7.5 Peripheral Reset 1.7.6 EMIF and USB Byte Access 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Contents Contents...
  • Page 4 1-45. DMAn Channel Event Source Register 2 (DMAnCESR2) [1C1Bh, 1C1Dh, 1C37h, and 1C39h] 1-46. Peripheral Software Reset Counter Register (PSRCR) [1C04h] 1-47. Peripheral Reset Control Register (PRCR) [1C05h] List of Figures List of Figures SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 5 1-48. EMIF System Control Register (ESCR) [1C33h] 1-49. EMIF Clock Divider Register (ECDR) [1C26h] SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated List of Figures...
  • Page 6 1-45. RTCPMGT Register Bit Descriptions Field Descriptions 1-46. LDOCNTL Register Bit Descriptions Field Descriptions 1-47. LDO Controls Matrix List of Tables List of Tables SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 7 1-61. Effect of USBSCR BYTEMODE Bits on USB Access 1-62. EMIF System Control Register (ESCR) Field Descriptions 1-63. EMIF Clock Divider Register (ECDR) Field Descriptions SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated List of Tables...
  • Page 8 List of Tables SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...

  • Page 9: Preface

    SPI supports multi-chip operation of up to four SPI slave devices. The SPI can operate as a master device only. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated Preface Read This First Read This First...
  • Page 10 TMS320C5515 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control. Read This First SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 11 SPRABB6— FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs This document describes FFT computation on the TMS320VC5505 and TMS320C5505/15 DSPs devices. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Related Documentation From Texas Instruments Copyright © 2010, Texas Instruments Incorporated Read This First...
  • Page 12 Read This First SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...

  • Page 13: System Control

    128 KB ROM Multiplexing Switched Central Resource (SCR) Serial Interfaces UART Connectivity USB 2.0 GP Timer PHY (HS) (x2) [DEVICE] Copyright © 2010, Texas Instruments Incorporated Chapter 1 System Control Program/Data Storage NAND, NOR, MMC/SD (x2) SRAM, mSDRAM System GP Timer LDOs...

  • Page 14: 1.1.2 Cpu Core

    512-pt FFT/iFFT Uint16 hwafft_512pts( Int32 *data,Int32 *scratch, Uint16 fft_flag, Uint16 scale_flag); 1024-pt FFT/IFFT Uint16 hwafft_1024pts( Int32 *data,Int32 *scratch, Uint16 fft_flag, Uint16 scale_flag); SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 15: Power Management

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback ): ANA_LDO ): DSP_LDO ): USB_LDO DDA1P3 and V DDA_ANA DDA_PLL DDA1P3 , USB_V , and USB_V DDOSC DDA3P3 Copyright © 2010, Texas Instruments Incorporated Introduction ), SAR, and power DDA_PLL DDPLL System Control...

  • Page 16: System Memory

    DMA controllers, and the USB. The DSP memory map as seen by these modules is illustrated in Figure 1-2. System Control SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 17: Dsp Memory Map

    00 4000h - 00 5FFFh 00 6000h - 00 7FFFh 00 8000h - 00 9FFFh 00 A000h - 00 BFFFh Copyright © 2010, Texas Instruments Incorporated System Memory DMA/USB Controller Byte Address Range 0001 00C0h - 0001 1FFFh 0001 2000h - 0001 3FFFh...

  • Page 18: Saram Blocks

    04 A000h - 04 BFFFh 04 C000h - 04 DFFFh 04 E000h - 04 FFFFh SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com DMA/USB Controller Byte Address Range 0001 C000h - 0001 DFFFh...

  • Page 19: Sarom Blocks

    FE 8000h - FE FFFFh FF 0000h - FF 7FFFh FF 8000h - FF FFFFh Section 1.7.3.4. Copyright © 2010, Texas Instruments Incorporated System Memory CPU Word Address Range 7F 0000h - 7F 3FFFh 7F 4000h - 7F 7FFFh 7F 8000h - 7F BFFFh...

  • Page 20: 1.2.2 I/O Memory Map

    The RTC oscillator generates a clock when a 32.768-KHz crystal is connected to the RTC_XI and System Control (Section 1.7.5.2) and the peripheral clock gating SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 21 SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback ) must be powered all the time but the 32.768-KHz crystal can be DDRTC Copyright © 2010, Texas Instruments Incorporated Device Clocking DDRTC System Control...

  • Page 22: Dsp Clocking Diagram

    PCGCR1[I2CCG] PCGCR1[UARTCG] UART PCGCR1[TMR2CG] Timer2 PCGCR1[TMR1CG] Timer1 PCGCR1[TMR0CG] Timer0 PCGCR1[MMCSD1CG] MMC/SD1 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com ST3_55[CLKOFF] SYSCLK CLKOUT ICR[HWAI] FFT Hardware Accelerator ICR[MPORTI] MPORT Clock ICR[XPORTI] XPORT Clock ICR[IPORTI]...

  • Page 23: 1.3.2 Clock Domains

    1-4) features a software-programmable PLL multiplier and several Section 1.4.3.1), the entire clock generator is bypassed, and the frequency 1.4.3.2), the input frequency can be both multiplied and divided to Copyright © 2010, Texas Instruments Incorporated System Clock Generator System Control...

  • Page 24: 1.4.2 Functional Description

    SYSCLK Frequency CLKREF ´ CLKREF RDRATIO + 4 CLKREF ´ CLKREF SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com SYSCLK Output Divider CGCR4. [OUTDIVEN] CCR2. [SYSCLKSEL] Table 1-10...

  • Page 25: Clkout Control Source Select Register (Ccssr) [1C24H]

    CLKOUT pin outputs USB PLL output clock. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback for more details on the PLL_MODE of the clock generator. Figure 1-5 Table 1-6). Reserved Copyright © 2010, Texas Instruments Incorporated System Clock Generator R/W-Bh System Control...

  • Page 26: 1.4.3 Configuration

    Logic within the clock generator ensures that there are no clock glitches during the transition from PLL MODE to BYPASS MODE and vice versa. System Control Section 1.4.3.1 for more information on the bypass mode of SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 27: Clock Generator Control Register Bits Used In Bypass Mode

    RTC clock = 32.768 kHz Section 1.4.4. Role in Bypass Mode Allows you to switch to the PLL or bypass modes. Determines whether reference divider should be bypassed or used. Copyright © 2010, Texas Instruments Incorporated System Clock Generator System Control...

  • Page 28: Pll Clock Frequency Ranges

    Specifies the divider ratio of the output divider. = 1.05 V 11.289 12.288 32.768 32.0 60 or 75 Figure SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 1-10 lists the = 1.3 V UNIT 11.28 12.28 32.76 32.0...

  • Page 29: 1.4.4 Clock Generator Registers

    Clock Generator Control Register 3 Clock Generator Control Register 4 Clock Configuration Register 1 Clock Configuration Register 2 Copyright © 2010, Texas Instruments Incorporated System Clock Generator PLL Output Frequency 32.768KHz x (173h+4) = 12.288 MHz 32.768KHz x (E4Ah + 4)/3 = 40.00 MHz 32.768KHz x (723h + 4) = 60.00 MHz...

  • Page 30: Clock Generator Control Register 1 (Cgcr1) [1C20H]

    ). When this bit is set to 0, the reference clock to the PLL is divided by the PLLIN CLKREF / (RDRATIO+4)). The RDRATIO bits specify the divider value. PLLIN CLKIN SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table 1-13. R/W-0 and described in Table 1-14.

  • Page 31: Clock Generator Control Register 3 (Cgcr3) [1C22H]

    The output divider is bypassed. The output divider is enabled. Reserved. Divider ratio bits for the output divider of the PLL. Divider value = ODRATIO + 1. Copyright © 2010, Texas Instruments Incorporated System Clock Generator and described in Table 1-15.

  • Page 32: Clock Configuration Register 1 (Ccr1) [1C1Eh]

    PLL mode is selected. System Control Figure 1-10 Reserved Figure 1-11 SYSCLKSRC Reserved CLKSELSTAT R/W-0 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table 1-17. SDCLK_EN R/W-0 and described in Table 1-18.

  • Page 33: Power Management

    The operating voltage and/or slew rate of the I/O pins can be reduced (at the expense of performance) to decrease I/O power consumption. The USB peripheral can be powered-down when not being used. Copyright © 2010, Texas Instruments Incorporated Power Management Description ) and USB Core (USB_V , USB_V...

  • Page 34: Clock Management

    This domain powers LDOs, POR comparator, and I/O supply for some pins. Nominal supply voltage is 1.8 V through 3.6 V. Note: This domain must be always powered for proper operation. SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...
  • Page 35 MPORT: this port is used by the four DMAs and the USB's CDMA when accessing SARAM or DARAM. • HWA: this port is the hardware accelerator (FFT coprocessor). It shares all CPU buses. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Power Management System Control...

  • Page 36: Idle Configuration Register (Icr) [0001H]

    CPU is disabled after execution of an IDLE instruction. System Control Table 1-22 describes the read-only bits of ISTR. Reserved R/W-0 IDLECFG R/W-0 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com HWAI IPORTI R/W-0 R/W-0 CPUI R/W-0 Submit Documentation Feedback...

  • Page 37: Idle Status Register (Istr) [0002H]

    Submit Documentation Feedback Reserved Reserved Section Requirements Before Going to Idle No requirements. No requirements. DMA controllers, LCD, and USB CDMA must not be accessing DARAM or SARAM. Copyright © 2010, Texas Instruments Incorporated Power Management HWAIS IPORTIS CPUIS 1.5.3.2. System Control...
  • Page 38 See the peripheral-specific user's guide for more details on these additional power saving features. System Control Requirements Before Going to Idle CPU CPUI must also be set. 1.5.3.1.2). Section SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com 1.5.3.2.3. Submit Documentation Feedback...

  • Page 39: Peripheral Clock Gating Configuration Register 1 (Pcgcr1) [1C02H]

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback TMR1CG EMIFCG TMR0CG R/W-0 R/W-0 MMCSD0CG DMA0CG UARTCG R/W-0 R/W-0 Copyright © 2010, Texas Instruments Incorporated Power Management Figure 1-14 and described in I2S1CG I2S0CG R/W-0 R/W-0 R/W-0 SPICG I2S3CG R/W-0...
  • Page 40 I2S3 clock gate control bit. This bit is used to enable and disable the I2S3 peripheral clock. Peripheral clock is active. Peripheral clock is disabled. System Control SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 41: Peripheral Clock Gating Configuration Register 2 (Pcgcr2) [1C03H]

    Peripheral clock is active. Peripheral clock is disabled. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Reserved DMA2CG DMA1CG R/W-0 R/W-0 Copyright © 2010, Texas Instruments Incorporated Power Management Figure 1-15 and described in USBCG SARCG LCDCG R/W-0 R/W-0...

  • Page 42: Peripheral Clock Stop Request/Acknowledge Register (Clkstop) [1C3Ah]

    PCGCR2, then set USBCKLSTPREQ to 0. Normal operating mode. Request permission to stop the peripheral clock. SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Figure 1-16 R/W-1 R/W-1...
  • Page 43 1 (PCGCR1). When enabling the EMIF internal clock, enable the clock through PCGCR1, then set EMFCKLSTPREQ to 0. Normal operating mode. Request permission to stop the peripheral clock. Section 1.4.2.2 Copyright © 2010, Texas Instruments Incorporated Power Management provides more information on System Control...

  • Page 44: Usb System Control Register (Usbscr) [1C32H]

    These comparators can be disabled for power savings when not needed. USB VBUS session end comparator is disabled. USB VBUS session end comparator is enabled. SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table 1-27.
  • Page 45 Word accesses by the CPU are allowed. Byte accesses by the CPU are allowed (high byte is selected). Byte accesses by the CPU are allowed (low byte is selected). Reserved. Copyright © 2010, Texas Instruments Incorporated Power Management (RTCPMGT) System Control...

  • Page 46: Static Power Management

    Clock output disabled. Clock output enabled. System Control and described in Table 1-28. WU_DOUT WU_DIR RW-0 RW-0 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com BG_PD LDO_PD RTCCLKOUTEN RW-0 RW-0 RW-0 Submit Documentation Feedback...

  • Page 47: Rtc Interrupt Flag Register (Rtcintfl) [1920H]

    Periodic Millisecond event occurred (write 1 to clear). SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Figure 1-19 Reserved DAYFL HOURFL Copyright © 2010, Texas Instruments Incorporated Power Management and described in Table 1-29. MINFL SECFL MSFL...

  • Page 48: Ram Sleep Mode Control Register1 [0X1C28]

    DARAM2 DARAM1 SLPZVSS SLPZVDD R/W+1 R/W+1 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Voltage 1.05 V or 1.3 V 1.05 V or 1.3 V 1.05 V or 1.3 V Figure 1-20 through...

  • Page 49: Ram Sleep Mode Control Register2 [0X1C2A]

    R/W+1 SARAM30 SARAM29 SARAM29 SLPZVSS SLPZVDD SLPZVSS R/W+1 R/W+1 SARAM26 SARAM25 SARAM25 SLPZVSS SLPZVDD SLPZVSS R/W+1 R/W+1 Copyright © 2010, Texas Instruments Incorporated Power Management SARAM4 SARAM4 SLPZVDD SLPZVSS R/W+1 R/W+1 R/W+1 SARAM0 SARAM0 SLPZVDD SLPZVSS R/W+1 R/W+1 R/W+1 SARAM12...

  • Page 50: Power Configurations

    All clock domains Turn on all power enabled domains Enable all clock domains SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Available Methods for Changing/Exiting Clock and Power Configuration A. RTC interrupt B. WAKEUP pin A.
  • Page 51 DSP is completely reset and the state of the DSP before going into IDLE2 is lost. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Section 1.5.3.4. Section 1.5.3.2 Copyright © 2010, Texas Instruments Incorporated Power Management for more details on setting the System Control...
  • Page 52 1.5.3.3. You can also enable the clock ) is ON, it can be set to two voltages: 1.3 V or 1.05 V (nominal). The SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com for more details on setting the minimum rating (1.05 V - 5% =...

  • Page 53: Interrupts

    0xA8 GPIO aggregated interrupt 0xB0 EMIF error interrupt 0xB8 I2C interrupt 0xC0 Bus error interrupt 0xC8 Data log interrupt 0xD0 Real-time operating system interrupt 0xD8 Software interrupt #27 Copyright © 2010, Texas Instruments Incorporated Interrupts Table 1-32. FUNCTION System Control...

  • Page 54: Ifr And Ier Registers

    Figure 1-25. IFR0 and IER0 Bit Locations PROG3 R/W-0 R/W-0 TINT INT1 R/W-0 R/W-0 Table 1-33. IFR0 and IER0 Bit Descriptions SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com FUNCTION Reserved PROG2 R/W-0 R/W-0 R/W-0 INT0 Reserved...

  • Page 55: Interrupt Timing

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Table 1-34. Figure 1-26. IFR1 and IER1 Bit Locations R/W-0 R/W-0 Table 1-34. IFR1 and IER1 Bit Descriptions Copyright © 2010, Texas Instruments Incorporated Interrupts RTOS DLOG BERR R/W-0 R/W-0 R/W-0...

  • Page 56: Timer Interrupt Aggregation Flag Register (Tiafr) [1C14H]

    You can determine which DMA channel generated the interrupt by reading the bits of the DMA interrupt flag register (DMAIFR). For more information, see the TMS320VC5505/VC5504 DSP Direct Memory Access (DMA) Controller User's Guide (SPRUFO9). System Control SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 57: System Configuration And Control

    Die ID Register 2 Die ID Register 3 Die ID Register 4 Die ID Register 5 Die ID Register 6 Die ID Register 7 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control Section Section 1.7.2.1 Section 1.7.2.2 Section 1.7.2.3 Section 1.7.2.4...

  • Page 58: Die Id Register 0 (Dieidr0) [1C40H]

    DIEID1 Description Reserved. Die ID bits. Figure 1-29 and described in DIEID2 Description Die ID bits. SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 1-36. Table 1-37. Table 1-38. Submit Documentation Feedback...

  • Page 59: Die Id Register 3 (Dieidr3[15:0]) [1C43H]

    Description Silicon Revision Silicon 2.0 Die ID bits. Figure 1-31 and described in Figure 1-32 and described in Reserved Copyright © 2010, Texas Instruments Incorporated System Configuration and Control Table 1-39. DIEID3 Table 1-40. DIEID4 Table 1-41.

  • Page 60: Die Id Register 6 (Dieidr6) [1C46H]

    Figure 1-33 and described in Reserved Figure 1-34 and described in CHECKSUM Description Reserved. Checksum bits. Reserved. SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 1-42. Table 1-43. Reserved Submit Documentation Feedback...

  • Page 61: Device Configuration

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Figure 1-35 SP1MODE R/W-00 A19_MODE A18_MODE A17_MODE R/W-0 R/W-0 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control and described in Table 1-44. SP0MODE R/W-00 A16_MODE A15_MODE R/W-0...

  • Page 62: Ebsr Register Bit Descriptions Field Descriptions

    24 (GP[24]) pin functions. Pin function is EMIF address pin 18 (EM_A[18]). Pin function is general-purpose input/output pin 24 (GP[24]). System Control SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 63: Rtc Power Management Register (Rtcpmgt) [1930H]

    1-36). When the LDOs are disabled via this pin. Figure 1-37). The USB _LDO is disabled at reset. Reserved WU_DOUT WU_DIR R/W-0 R/W-0 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control BG_PD LDO_PD RTCCLKOUTEN R/W-0 R/W-0 R/W-0 System Control...

  • Page 64: Rtcpmgt Register Bit Descriptions Field Descriptions

    Clock output disabled Clock output enabled System Control . WU_DIR must be configured as an input to allow the WAKEUP pin to DDRTC SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 65: Ldo Control Register (Ldocntl) [7004H]

    Table 1-47. LDO Controls Matrix LDOCNTL Register (0x7004) DSP_LDO_EN USB_LDO_EN Bit (Pin D12) Don't Care Don't Care Don't Care Don't Care High Copyright © 2010, Texas Instruments Incorporated System Configuration and Control DSP_LDO_V USB_LDO_EN R/W-0 R/W-0 ANA_LDO DSP_LDO USB_LDO System Control...

  • Page 66: Output Slew Rate Control Register (Osrcr) [1C16H]

    EMIF pin output slew rate bits. These bits set the slew rate for the EMIF pins. Slow slew rate Fast slew rate System Control Figure 1-38 CLKOUTSR SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table 1-48. Reserved EMIFSR...

  • Page 67: Pull-Down Inhibit Register 1 (Pdinhibr1) [1C17H]

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Figure 1-39 S14PD S13PD R/W-1 R/W-1 S04PD S03PD R/W-1 R/W-1 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control and described in Table 1-49. S12PD S11PD S10PD R/W-1 R/W-1 R/W-1...

  • Page 68: Pull-Down Inhibit Register 2 (Pdinhibr2) [1C18H]

    Reserved. System Control Figure 1-40 RESETPU EMU01PU R/W-0 R/W-0 A19PD A18PD R/W-1 R/W-1 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com and described in Table 1-50. TDIPU TMSPU TCKPU R/W-0 R/W-0 R/W-0 A17PD...

  • Page 69: Pull-Down Inhibit Register 3 (Pdinhibr3) [1C19H]

    SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Figure 1-41 PD12PD PD11PD R/W-1 R/W-1 PD4PD PD3PD R/W-1 R/W-1 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control and described in Table 1-51. PD10PD PD9PD PD8PD R/W-1 R/W-1 R/W-1...

  • Page 70: Dma Controller Configuration

    Lowercase, italicized, n is an integer, 0-3, representing each of the 4 DMAs. • Lowercase, italicized, m is an integer, 0-3, representing each of the 4 channels within each DMA. System Control SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Submit Documentation Feedback...

  • Page 71: Channel Synchronization Events For Dma Controllers

    DMA1 Channel Event Source Register 2 DMA2 Channel Event Source Register 1 DMA2 Channel Event Source Register 2 DMA3 Channel Event Source Register 1 DMA3 Channel Event Source Register 2 Copyright © 2010, Texas Instruments Incorporated System Configuration and Control DMA2 DMA3 Synchronization Synchronization...

  • Page 72: Dma Interrupt Flag Register (Dmaifr) [1C30H]

    DMA0CH2IF RW-0 RW-0 DMA3CH0IE DMA2CH3IE DMA2CH2IE RW-0 RW-0 DMA1CH0IE DMA0CH3IE DMA0CH2IE RW-0 RW-0 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com DMA2CH1IF DMA2CH0IF RW-0 RW-0 RW-0 DMA0CH1IF DMA0CH0IF RW-0 RW-0 RW-0 DMA2CH1IE DMA2CH0IE...

  • Page 73: Peripheral Reset

    Table 1-52 for a list of available synchronization event options. Table 1-52 for a list of available synchronization event options. Copyright © 2010, Texas Instruments Incorporated System Configuration and Control Table 1-52. Multiple DMAs and CH0EVT...

  • Page 74: Peripheral Software Reset Counter Register (Psrcr) [1C04H]

    0. Always initialize this field with a value of at least 08h. Figure 1-47 Reserved DMA_RST USB_RST SAR_RST R/W-0 R/W-0 SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com Table 1-58 and described in and described in Table 1-59. PG1_RST I2C_RST...

  • Page 75: Emif And Usb Byte Access

    NOTE: The BYTEMODE bits of the EMIF system control register should only be used for controlling CPU accesses to NAND Flash devices and EMIF registers. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated System Configuration and Control Table 1-60 Table 1-61...

  • Page 76: Effect Of Bytemode Bits On Emif Accesses

    Only the upper byte of the register is accessed Only the lower byte of the register is accessed Figure 1-48 and described in Reserved SPRUFX5A – October 2010 – Revised November 2010 Copyright © 2010, Texas Instruments Incorporated www.ti.com 1.5.3.4.2. Table 1-62. BYTEMODE...

  • Page 77: Emif Clock Divider Register (Ecdr) [1C26H]

    EMIF operates at the same rate as the peripheral clock. SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Figure 1-49 and described in Reserved Copyright © 2010, Texas Instruments Incorporated System Configuration and Control Table 1-63. EDIV R/W-1...

  • Page 78: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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