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TMS3320C5515
Texas Instruments TMS3320C5515 Processor Manuals
Manuals and User Guides for Texas Instruments TMS3320C5515 Processor. We have
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Texas Instruments TMS3320C5515 Processor manual available for free PDF download: User Manual
Texas Instruments TMS3320C5515 User Manual (78 pages)
DSP System - digital signal processor
Brand:
Texas Instruments
| Category:
Processor
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
9
Read this First
9
System Control
13
Introduction
13
1.1.1 Block Diagram
13
Functional Block Diagram
13
1.1.2 CPU Core
14
1.1.3 FFT Hardware Accelerator
14
Power Management
15
1.1.5 Peripherals
15
System Memory
16
1.2.1 Program/Data Memory Map
16
DSP Memory Map
17
DARAM Blocks
17
SARAM Blocks
18
SAROM Blocks
19
1.2.2 I/O Memory Map
20
I/O & Memory Map
20
Device Clocking
20
1.3.1 Overview
20
DSP Clocking Diagram
22
1.3.2 Clock Domains
23
System Clock Generator
23
1.4.1 Overview
23
1.4.2 Functional Description
24
Clock Generator
24
PLL Output Frequency Configuration
24
CLKOUT Control Source Select Register (CCSSR) [1C24H]
25
CLKOUT Control Source Select Register (CCSSR) Field Descriptions
25
1.4.3 Configuration
26
Clock Generator Control Register Bits Used in BYPASS MODE
27
Output Frequency in Bypass Mode
27
Clock Generator Control Register Bits Used in PLL Mode
27
PLL Clock Frequency Ranges
28
1.4.4 Clock Generator Registers
29
Examples of Selecting a PLL MODE Frequency, When CLK_SEL=L
29
Clock Generator Control Register 1 (CGCR1) [1C20H]
30
Clock Generator Control Register 2 (CGCR2) [1C21H]
30
Clock Generator Control Register 1 (CGCR1) Field Descriptions
30
Clock Generator Control Register 2 (CGCR2) Field Descriptions
30
Clock Generator Control Register 3 (CGCR3) [1C22H]
31
Clock Generator Control Register 4 (CGCR4) [1C23H]
31
Clock Generator Control Register 3 (CGCR3) Field Descriptions
31
Clock Generator Control Register 4 (CGCR4) Field Descriptions
31
Clock Configuration Register 1 (CCR1) [1C1Eh]
32
Clock Configuration Register 2 (CCR2) [1C1Fh]
32
Clock Configuration Register 1 (CCR1) Field Descriptions
32
Clock Configuration Register 2 (CCR2) Field Descriptions
32
Power Management
33
Overview
33
Power Domains
33
Power Management Features
33
Clock Management
34
DSP Power Domains
34
Idle Configuration Register (ICR) [0001H]
36
Idle Configuration Register (ICR) Field Descriptions
36
Idle Status Register (ISTR) [0002H]
37
Idle Status Register (ISTR) Field Descriptions
37
CPU Clock Domain Idle Requirements
37
Peripheral Clock Gating Configuration Register 1 (PCGCR1) [1C02H]
39
Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions
39
Peripheral Clock Gating Configuration Register 2 (PCGCR2) [1C03H]
41
Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions
41
Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah]
42
Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions
42
USB System Control Register (USBSCR) [1C32H]
44
USB System Control Register (USBSCR) Field Descriptions
44
Static Power Management
46
RTC Power Management Register (RTCPMGT) [1930H]
46
RTC Power Management Register (RTCPMGT) Field Descriptions
46
RTC Interrupt Flag Register (RTCINTFL) [1920H]
47
RTC Interrupt Flag Register (RTCINTFL) Field Descriptions
47
RAM Sleep Mode Control Register1 [0X1C28]
48
On-Chip Memory Standby Modes
48
RAM Sleep Mode Control Register2 [0X1C2A]
49
RAM Sleep Mode Control Register3 [0X1C2B]
49
RAM Sleep Mode Control Register4 [0X1C2C]
49
RAM Sleep Mode Control Register5 [0X1C2D]
49
Power Configurations
50
Interrupts
53
Interrupt Table
53
IFR and IER Registers
54
IFR0 and IER0 Bit Locations
54
IFR0 and IER0 Bit Descriptions
54
Interrupt Timing
55
IFR1 and IER1 Bit Locations
55
IFR1 and IER1 Bit Descriptions
55
Timer Interrupt Aggregation Flag Register (TIAFR) [1C14H]
56
GPIO Interrupt Enable and Aggregation Flag Registers
56
DMA Interrupt Enable and Aggregation Flag Registers
56
System Configuration and Control
57
Overview
57
Device Identification
57
Die ID Registers
57
Die ID Register 0 (DIEIDR0) [1C40H]
58
Die ID Register 1 (DIEIDR1) [1C41H]
58
Die ID Register 2 (DIEIDR2) [1C42H]
58
Die ID Register 0 (DIEIDR0) Field Descriptions
58
Die ID Register 1 (DIEIDR1) Field Descriptions
58
Die ID Register 2 (DIEIDR2) Field Descriptions
58
Die ID Register 3 (DIEIDR3[15:0]) [1C43H]
59
Die ID Register 4 (DIEIDR4) [1C44H]
59
Die ID Register 5 (DIEIDR5) [1C45H]
59
Die ID Register 3 (DIEIDR3[15:0]) Field Descriptions
59
Die ID Register 4 (DIEIDR4) Field Descriptions
59
Die ID Register 5 (DIEIDR5) Field Descriptions
59
Die ID Register 6 (DIEIDR6) [1C46H]
60
Die ID Register 7 (DIEIDR7) [1C47H]
60
Die ID Register 6 (DIEIDR6) Field Descriptions
60
Die ID Register 7 (DIEIDR7) Field Descriptions
60
Device Configuration
61
External Bus Selection Register (EBSR) [1C00H]
61
EBSR Register Bit Descriptions Field Descriptions
62
RTC Power Management Register (RTCPMGT) [1930H]
63
RTCPMGT Register Bit Descriptions Field Descriptions
64
LDO Control Register (LDOCNTL) [7004H]
65
LDOCNTL Register Bit Descriptions Field Descriptions
65
LDO Controls Matrix
65
Output Slew Rate Control Register (OSRCR) [1C16H]
66
Output Slew Rate Control Register (OSRCR) Field Descriptions
66
Pull-Down Inhibit Register 1 (PDINHIBR1) [1C17H]
67
Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions
67
Pull-Down Inhibit Register 2 (PDINHIBR2) [1C18H]
68
Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions
68
Pull-Down Inhibit Register 3 (PDINHIBR3) [1C19H]
69
Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions
69
DMA Controller Configuration
70
Channel Synchronization Events for DMA Controllers
71
System Registers Related to the DMA Controllers
71
DMA Interrupt Flag Register (DMAIFR) [1C30H]
72
DMA Interrupt Enable Register (DMAIER) [1C31H]
72
DMA Interrupt Flag Register (DMAIFR) Field Descriptions
72
DMA Interrupt Enable Register (DMAIER) Field Descriptions
72
Peripheral Reset
73
Dman Channel Event Source Register 1 (Dmancesr1) [1C1Ah, 1C1Ch, 1C36H, and 1C38H]
73
Dman Channel Event Source Register 2 (Dmancesr2) [1C1Bh, 1C1Dh, 1C37H, and 1C39H]
73
Dman Channel Event Source Register 1 (Dmancesr1) Field Descriptions
73
Dman Channel Event Source Register 2 (Dmancesr2) Field Descriptions
73
Peripheral Software Reset Counter Register (PSRCR) [1C04H]
74
Peripheral Reset Control Register (PRCR) [1C05H]
74
Peripheral Software Reset Counter Register (PSRCR) Field Descriptions
74
Peripheral Reset Control Register (PRCR) Field Descriptions
74
EMIF and USB Byte Access
75
Effect of BYTEMODE Bits on EMIF Accesses
76
Effect of USBSCR BYTEMODE Bits on USB Access
76
EMIF System Control Register (ESCR) Field Descriptions
76
EMIF Clock Divider Register (ECDR) Field Descriptions
77
EMIF Clock Divider Register (ECDR) [1C26H]
77
Important Notice
78
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