Texas Instruments SM320C6455-EP Manuals

Manuals and User Guides for Texas Instruments SM320C6455-EP. We have 1 Texas Instruments SM320C6455-EP manual available for free PDF download: Data Manual

Texas Instruments SM320C6455-EP Data Manual

Texas Instruments SM320C6455-EP Data Manual (254 pages)

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Brand: Texas Instruments | Category: Processor | Size: 2 MB

Table of Contents

Table of Contents
3
1 Features

7
2 Device Overview

11
- Device Characteristics
  11
- CPU (DSP Core) Description
  12
- Memory Map Summary
  15
- Boot Sequence
  17
  - Boot Modes Supported
    17
  - 2Nd-Level Bootloaders
    19
- Pin Assignments
  20
  - Pin Map
    20
- Signal Groups Description
  24
- Terminal Functions
  30
- Development
  55
  - Development Support
    55
  - Device Support
    55
    
    Device and Development-Support Tool Nomenclature
    55
    
    Documentation Support
    56
3 Device Configuration

59
4 System Interconnect

81
5 C64X+ Megamodule

87
- Memory Architecture
  87
- Memory Protection
  90
- Bandwidth Management
  90
- Power-Down Control
  91
- Megamodule Resets
  91
- Megamodule Revision
  92
- C64X+ Megamodule Register Description(S)
  93
- Device Operating Conditions
  101
- Absolute Maximum Ratings over Operating Case Temperature Range (Unless Otherwise Noted)
  101
- Recommended Operating Conditions
  101
- Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  103
- C64X+ Peripheral Information and Electrical Specifications
  
  105
  - Parameter Information
    105
    
    V Signal Transition Levels
    105
    
    V Signal Transition Rates
    105
    
    Timing Parameters and Board Routing Analysis
    106
  - Recommended Clock and Control Signal Transition Behavior
    107
  - Power Supplies
    107
    
    Power-Down Operation
    107
    
    Power-Supply Decoupling
    107
    
    Power-Supply Sequencing
    107
    
    Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins
    108
  - Enhanced Direct Memory Access (EDMA3) Controller
    109
    
    EDMA3 Channel Synchronization Events
    110
    
    EDMA3 Device-Specific Information
    110
    
    EDMA3 Peripheral Register Description(S)
    111
  - Interrupts
    124
    
    Interrupt Sources and Interrupt Controller
    124
    
    External Interrupts Electrical Data/Timing
    127
  - Reset Controller
    128
    
    Power-On Reset (por Pin)
    128
    
    Warm Reset (RESET Pin)
    129
    
    CPU Reset
    130
    
    Max Reset
    130
    
    System Reset
    130
    
    Reset Priority
    131
    
    Reset Controller Register
    132
    
    Reset Type Status Register Description
    132
    
    Reset Electrical Data/Timing
    133
  - PLL1 and PLL1 Controller
    136
    
    Internal Clocks and Maximum Operating Frequencies
    137
    
    PLL1 Controller Device-Specific Information
    137
    
    PLL1 Controller Operating Modes
    138
    
    PLL1 Stabilization, Lock, and Reset Times
    138
    
    PLL1 Controller Memory Map
    139
    
    PLL1 Control Register
    140
    
    PLL1 Controller Register Descriptions
    140
    
    PLL Multiplier Control Register
    141
    
    PLL Pre-Divider Control Register
    142
    
    PLL Controller Divider 4 Register
    143
    
    PLL Controller Divider 5 Register
    144
    
    PLL Controller Command Register
    145
    
    PLL Controller Status Register
    146
    
    PLL Controller Clock Align Control Register
    147
    
    PLLDIV Ratio Change Status Register
    148
    
    SYSCLK Status Register
    149
    
    PLL1 Controller Input and Output Clock Electrical Data/Timing
    150
  - PLL2 and PLL2 Controller
    151
    
    Internal Clocks and Maximum Operating Frequencies
    152
    
    PLL2 Controller Device-Specific Information
    152
    
    PLL2 Controller Operating Modes
    152
    
    PLL2 Controller Memory Map
    153
    
    PLL2 Controller Register Descriptions
    153
    
    Sprs462B – September 2007 – Revised January
    153
    
    PLL Controller Divider 1 Register
    154
    
    PLL Controller Command Register
    155
    
    PLL Controller Clock Align Control Register
    156
    
    PLL Controller Status Register
    156
    
    PLLDIV Ratio Change Status Register
    157
    
    SYSCLK Status Register
    158
    
    PLL2 Controller Input Clock Electrical Data/Timing
    159
  - DDR2 Memory Controller
    160
    
    DDR2 Memory Controller Device-Specific Information
    160
    
    DDR2 Memory Controller Electrical Data/Timing
    161
    
    DDR2 Memory Controller Peripheral Register Description(S)
    161
  - External Memory Interface a (EMIFA)
    162
    
    EMIFA Device-Specific Information
    162
    
    EMIFA Peripheral Register Description(S)
    163
    
    EMIFA Electrical Data/Timing
    164
    
    Asynchronous Memory Timing
    165
    
    Programmable Synchronous Interface Timing
    168
    
    HOLD/HOLDA Timing
    171
    
    BUSREQ Timing
    172
  - I2C Peripheral
    173
    
    I2C Device-Specific Information
    173
    
    I2C Peripheral Register Description(S)
    175
    
    I2C Electrical Data/Timing
    176
    
    Inter-Integrated Circuits (I2C) Timing
    176
  - Host-Port Interface (HPI) Peripheral
    179
    
    HPI Device-Specific Information
    179
    
    HPI Peripheral Register Description(S)
    179
    
    HPI Electrical Data/Timing
    180
  - Multichannel Buffered Serial Port (Mcbsp)
    190
    
    Mcbsp Device-Specific Information
    191
    
    Mcbsp Peripheral Register Description(S)
    191
    
    Mcbsp Electrical Data/Timing
    193
    
    Multichannel Buffered Serial Port (Mcbsp) Timing
    193
  - Ethernet MAC (EMAC)
    200
    
    EMAC Device-Specific Information
    201
    
    EMAC Peripheral Register Description(S)
    204
    
    EMAC Electrical Data/Timing
    208
    
    EMAC MII and GMII Electrical Data/Timing
    208
    
    EMAC RMII Electrical Data/Timing
    211
    
    EMAC RGMII Electrical Data/Timing
    213
    
    Management Data Input/Output (MDIO)
    216
    
    MDIO Device-Specific Information
    216
    
    MDIO Peripheral Register Description(S)
    216
    
    MDIO Electrical Data/Timing
    217
  - Timers
    218
    
    Timers Device-Specific Information
    218
    
    Timers Peripheral Register Description(S)
    218
    
    Timers Electrical Data/Timing
    219
  - Enhanced Viterbi-Decoder Coprocessor (VCP2)
    220
    
    VCP2 Device-Specific Information
    220
    
    VCP2 Peripheral Register Description(S)
    220
  - Enhanced Turbo Decoder Coprocessor (TCP2)
    221
    
    TCP2 Device-Specific Information
    221
    
    TCP2 Peripheral Register Description(S)
    222
  - Peripheral Component Interconnect (PCI)
    223
    
    PCI Device-Specific Information
    223
    
    PCI Peripheral Register Description(S)
    224
    
    PCI Electrical Data/Timing
    229
  - Utopia
    230
    
    UTOPIA Device-Specific Information
    230
    
    UTOPIA Peripheral Register Description(S)
    230
    
    UTOPIA Electrical Data/Timing
    231
  - Serial Rapidio (SRIO) Port
    234
    
    Serial Rapidio Device-Specific Information
    234
    
    Serial Rapidio Peripheral Register Description(S)
    234
    
    Serial Rapidio Electrical Data/Timing
    244
  - General-Purpose Input/Output (GPIO)
    246
    
    GPIO Device-Specific Information
    246
    
    GPIO Peripheral Register Description(S)
    246
    
    GPIO Electrical Data/Timing
    247
  - Emulation Features and Capability
    248
    
    Advanced Event Triggering (AET)
    248
    
    Trace
    248
    
    Ieee 1149.1 Jtag
    249
    
    JTAG Device-Specific Information
    249
    
    JTAG Electrical Data/Timing
    249
    
    JTAG Peripheral Register Description(S)
    249
Revision History

250
8 Mechanical Data

251
- Thermal Data
  251
- Packaging Information
  251
  - Packaging Information
    252
  - Important Notice
    254

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