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Texas Instruments TMS320C2XX User Manual

Digital signal processors (dsps)
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Table of Contents
TMS320C2xx
User's Guide
Literature Number: SPRU127B
Manufacturing Part Number: D412008-9761 revision A
January 1997
Printed on Recycled Paper

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  Summary of Contents for Texas Instruments TMS320C2XX

  • Page 1 TMS320C2xx User’s Guide Literature Number: SPRU127B Manufacturing Part Number: D412008-9761 revision A January 1997 Printed on Recycled Paper...
  • Page 2 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
  • Page 3: Read This First

    How to Use This Manual Chapter 1, Introduction , summarizes the TMS320 family of products and then introduces the key features of the TMS320C2xx generation of that family. Chapter 2, Architectural Overview , summarizes the ’C2xx architecture, providing information about the CPU, bus structure, memory, on-chip peripherals, and scanning logic.
  • Page 4 How to Use This Manual For this information: Addressing modes (for addressing data memory) Assembly language instructions Assembly language instructions of TMS320C1x, ’C2x, ’C2xx, and ’C5x compared Boot loader Clock generator Custom ROM from TI Emulator Features Input/output ports Interrupts Memory configuration Memory interfacing On-chip peripherals...
  • Page 5 Notational Conventions This document uses the following conventions: Program listings and program examples are shown in a special typeface. Here is a segment of a program listing: OUTPUT LDP In syntax descriptions, bold portions of a syntax should be entered as shown;...
  • Page 6 When ordering, please identify the document by its title and literature number. The following data sheets contain the electrical and timing specifications for the TMS320C2xx devices, as well as signal descriptions and pinouts for all of the available packages: TMS320C2xx data sheet (literature number SPRS025) TMS320F2xx data sheet (literature number SPRS050).
  • Page 7 TMS320C2xx Simulator Getting Started (literature number SPRU137) describes how to install the TMS320C2xx simulator and the C source debugger for the ’C2xx. The installation for MS-DOS , PC-DOS , SunOS , Solaris , and HP-UX TMS320C2xx Emulator Getting Started Guide (literature number SPRU209) tells you how to install the Windows 3.1 and Windows 95...
  • Page 8 Related Articles Related Articles “A Greener World Through DSP Controllers”, Panos Papamichalis, DSP & Multimedia Technology , September 1994. “A Single-Chip Multiprocessor DSP for Image Processing—TMS320C80”, Dr. Ing. Dung Tu, Industrie Elektronik , Germany, March 1995. “Application Guide with DSP Leading-Edge Technology”, Y. Nishikori, M. Hattori, T.
  • Page 9 Related Articles “Fixed or Floating? A Pointed Question in DSPs”, Jim Larimer and Daniel Chen, EDN , August 3, 1995. “Function-Focused Chipsets: Up the DSP Integration Core”, Panos Papamichalis, DSP & Multimedia Technology , March/April 1995. “GSM: Standard, Strategien und Systemchips”, Edgar Auslander, Elektronik Praxis , Germany, October 6, 1995.
  • Page 10 Trademarks Trademarks TI, 320 Hotline On-line, XDS510, XDS510PP, XDS510WS, and XDS511 are trademarks of Texas Instruments Incorporated. HP-UX is a trademark of Hewlett-Packard Company. Intel is a trademark of Intel Corporation. MS-DOS and Windows are registered trademarks of Microsoft Corporation.
  • Page 11 When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Technical Documentation Services, MS 702 P.O.
  • Page 12: Table Of Contents

    1.1.2 Typical Applications for the TMS320 Family TMS320C2xx Generation Key Features of the TMS320C2xx Architectural Overview Summarizes the TMS320C2xx architecture. Provides information about the CPU, bus structure, memory, on-chip peripherals, and scanning logic. ’C2xx Bus Structure Central Processing Unit 2.2.1 Central Arithmetic Logic Unit (CALU) and Accumulator 2.2.2...
  • Page 13 ARAU and Auxiliary Register Functions Status Registers ST0 and ST1 Memory and I/O Spaces Describes the configuration and use of the TMS320C2xx memory and I/O spaces. Includes memory/address maps and descriptions of the HOLD (direct memory access) operation and the on-chip boot loader.
  • Page 14 ..............Describes the TMS320C2xx hardware and software features used in controlling program flow, including program-address generation logic and interrupts.
  • Page 15 6.3.5 Examples of Indirect Addressing 6.3.6 Modifying Auxiliary Register Content Assembly Language Instructions Describes the TMS320C2xx assembly language instructions in alphabetical order. Begins with a summary of the TMS320C2xx instructions. Instruction Set Summary How To Use the Instruction Descriptions 7.2.1 Syntax .
  • Page 16 Synchronous Serial Port Describes the operation and control of the TMS320C2xx on-chip synchronous serial port. Overview of the Synchronous Serial Port Components and Basic Operation 9.2.1 Signals .............
  • Page 17 ..............Describes how the TMS320C209 differs from other TMS320C2xx devices and is a central resource for all the TMS320C209-specific control registers and configuration information.
  • Page 18 Submitting ROM Codes to TI Explains the process for submitting custom program code to TI for designing masks for the on-chip ROM on a TMS320 DSP. Design Considerations for Using XDS510 Emulator Describes the JTAG emulator cable and how to construct a 14-pin connector on your target system and how to connect the target system to the emulator.
  • Page 19 Figures 1–1 TMS320 Family ............. . . 2–1 Overall Block Diagram of the ’C2xx 2–2...
  • Page 20 5–5 INT2/INT3 Request Flow Chart 5–6 Maskable Interrupt Operation Flow Chart 5–7 ’C2xx Interrupt Flag Register (IFR) — Data-Memory Address 0006h 5–8 ’C2xx Interrupt Mask Register (IMR) — Data-Memory Address 0004h 5–9 ’C2xx Interrupt Control Register (ICR) — I/O-Space Address FFECh 5–10 Nonmaskable Interrupt Operation Flow Chart 6–1...
  • Page 21 Figures 11–2 ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h 11–3 ’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h 11–4 ’C209 Timer Control Register (TCR) — I/O Address FFFCh 11–5 ’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh C–1 Procedure for Generating Executable Files D–1...
  • Page 22 1–1 Typical Applications for TMS320 DSPs 1–2 ’C2xx Generation Summary 2–1 Program and Data Memory on the TMS320C2xx Devices 2–2 Serial Ports on the ’C2xx Devices 3–1 Product Shift Modes for the Product-Scaling Shifter 3–2 Bit Fields of Status Registers ST0 and ST1 4–1...
  • Page 23 Tables 9–1 SSP Interface Pins ............9–2 Run and Emulation Modes 9–3...
  • Page 24 4–1 An Interrupt Service Routine Supporting INT1 and HOLD 6–1 RPT Instruction Using Short-Immediate Addressing 6–2 ADD Instruction Using Long-Immediate Addressing 6–3 Using Direct Addressing with ADD (Shift of 0 to 15) 6–4 Using Direct Addressing with ADD (Shift of 16) 6–5 Using Direct Addressing with ADDC 6–6...
  • Page 25 Cautions Obtain the Proper Timing Information Do Not Write to Test/Emulation Addresses Obtain the Proper Timing Information Do Not Write to Reserved Addresses Do Not Write to Reserved Addresses Do Not Write to Reserved Addresses Initialize the DP in All Programs Do Not Write to Reserved Addresses xxvi .
  • Page 26: Introduction

    The TMS320C2xx (’C2xx) is one of several fixed-point generations of DSPs in the TMS320 family. The ’C2xx is source-code compatible with the TMS320C2x. Much of the code written for the ’C2x can be reassembled to run on a ’C2xx device. In addition, the ’C2xx generation is upward compatible with the ’C5x generation of DSPs.
  • Page 27: Tms320 Family

    1.1.1 History, Development, and Advantages of TMS320 DSPs In 1982, Texas Instruments introduced the TMS32010, the first fixed-point DSP in the TMS320 family. Before the end of the year, Electronic Products magazine awarded the TMS32010 the title “Product of the Year”. Today, the TMS320 family consists of these generations: ’C1x, ’C2x, ’C2xx, ’C5x, and...
  • Page 28: Tms320 Family

    TMS320 Family Figure 1–1. TMS320 Family Performance Introduction...
  • Page 29: Typical Applications For The Tms320 Family

    TMS320 Family 1.1.2 Typical Applications for the TMS320 Family Table 1–1 lists some typical applications for the TMS320 family of DSPs. The TMS320 DSPs offer adaptable approaches to traditional signal-processing problems such as filtering and vocoding. They also support complex applications that often require multiple operations to be performed simulta- neously.
  • Page 30: Tms320C2Xx Generation

    1.2 TMS320C2xx Generation Texas Instruments uses static CMOS integrated-circuit technology to fabricate the TMS320C2xx DSPs. The architectural design of the ’C2xx is based on that of the ’C5x. The operational flexibility and speed of the ’C2xx and ’C5x are a...
  • Page 31: Key Features Of The Tms320C2Xx

    Key Features of the TMS320C2xx 1.3 Key Features of the TMS320C2xx Key features on the various ’C2xx devices are: Speed: Code compatibility with other TMS320 fixed-point devices: Memory: CPU: Program control: 50-, 35-, or 25-ns execution time of a single-cycle instruction 20, 28.5, or 40 MIPS...
  • Page 32 On-chip scanning-logic circuitry (IEEE Standard 1149.1) for emulation and testing purposes Power: 5- or 3.3-V static CMOS technology Power-down mode to reduce power consumption Packages: 100-pin TQFP (thin quad flat pack) 80-pin TQFP for the ’C209 Key Features of the TMS320C2xx instructions better program/data Introduction...
  • Page 33: Architectural Overview

    Architectural Overview This chapter provides an overview of the architectural structure and compo- nents of the ’C2xx. The ’C2xx DSPs use an advanced, modified Harvard archi- tecture that maximizes processing power by maintaining separate bus struc- tures for program memory and data memory. The three main components of the ’C2xx are the central processing unit (CPU), memory, and on-chip periph- erals.
  • Page 34: Overall Block Diagram Of The 'C2Xx

    Architectural Overview Figure 2–1. Overall Block Diagram of the ’C2xx ROM/flash SARAM DARAM DARAM B1, B2 GREG DWAB DRAB PRDB Note: The I/O-mapped (peripheral) registers are not part of the core; they are accessed as shown in Figure 2–2 on page 2-4. PRDB DRDB NPAR...
  • Page 35: C2Xx Bus Structure

    2.1 ’C2xx Bus Structure Figure 2–2 shows a block diagram of the ’C2xx bus structure. The ’C2xx inter- nal architecture is built around six 16-bit buses: PAB. The program address bus provides addresses for both reads from and writes to program memory. DRAB.
  • Page 36: Bus Structure Block Diagram

    ’C2xx Bus Structure Figure 2–2. Bus Structure Block Diagram ROM/ flash External address bus External data bus On-chip peripherals/ registers mapped to I/O space Timer Wait-state generator Synchronous serial port UART Other I/O-mapped registers SARAM DARAM DRAB DWAB PRDB DRDB DWEB Central processing unit (CPU) Input...
  • Page 37: Central Processing Unit

    2.2 Central Processing Unit The CPU is the same on all the ’C2xx devices. The ’C2xx CPU contains: A 32-bit central arithmetic logic unit (CALU) A 32-bit accumulator Input and output data-scaling shifters for the CALU A 16-bit A product-scaling shifter Data-address generation logic, which includes eight auxiliary registers and an auxiliary register arithmetic unit (ARAU) Program-address generation logic...
  • Page 38: Multiplier

    Central Processing Unit 2.2.3 Multiplier The on-chip multiplier performs 16-bit with a 32-bit result. In conjunction with the multiplier, the ’C2xx uses the 16-bit temporary register (TREG) and the 32-bit product register (PREG). The TREG always supplies one of the values to be multiplied. The PREG receives the re- sult of each multiplication.
  • Page 39: Memory And I/O Spaces

    RAM (SARAM) and read-only memory (ROM) or flash memory. Table 2–1 shows how much ROM, flash memory, DARAM, and SARAM are available on the different ’C2xx devices. Table 2–1. Program and Data Memory on the TMS320C2xx Devices Memory Type ROM (words)
  • Page 40: Single-Access On-Chip Program/Data Ram

    If you want a custom ROM, you can provide the code or data to be pro- grammed into the ROM in object file format, and Texas Instruments will gener- ate the appropriate process mask to program the ROM. See Appendix D for...
  • Page 41: Flash Memory

    Memory and I/O Spaces 2.3.4 Flash Memory Some of the ’C2xx devices feature on-chip blocks of flash memory, which is electronically erasable and programmable, and non-volatile. Each block of flash memory will have a set of control registers that allow for erasing, pro- gramming, and testing of that block.
  • Page 42: Program Control

    Program Control Program Control 2.4 Program Control Several features provide program control: The program controller of the CPU decodes instructions, manages the pipeline, stores the status of operations, and decodes conditional opera- tions. Elements involved in program control are the program counter, the status registers, the stack, and the address-generation logic.
  • Page 43: On-Chip Peripherals

    2.5 On-Chip Peripherals All the ’C2xx devices have the same CPU, but different on-chip peripherals are connected to their CPUs. The on-chip peripherals featured on the ’C2xx de- vices are: Clock generator (an oscillator and a phase lock loop circuit) CLK register for turning the CLKOUT1 pin on and off Timer Wait-state generator...
  • Page 44: General-Purpose I/O Pins

    On-Chip Peripherals 2.5.5 General-Purpose I/O Pins The ’C2xx has pins that provide general-purpose input or output signals. All ’C2xx devices have a general-purpose input pin, BIO, and a general-purpose output pin, XF. Except for the ’C209, the ’C2xx devices also have pins IO0, IO1, IO2, and IO3, which are connected to corresponding bits (IO0–IO3) mapped into the on-chip I/O space.
  • Page 45: Scanning-Logic Circuitry

    ’C2xx devices, the serial scan path does not have boundary scan logic. Appendix E provides information to help you meet the design requirements of the Texas Instruments XDS510 emulator with respect to IEEE-1149.1 de- signs and discusses the XDS510 cable.
  • Page 46: Central Processing Unit

    Central Processing Unit This chapter describes the main components of the central processing unit (CPU). First, this chapter describes three fundamental sections of the CPU (see Figure 3–1): Input scaling section Multiplication section Central arithmetic logic section The chapter then describes the auxiliary register arithmetic unit (ARAU), which performs arithmetic operations independently of the central arithmetic logic section.
  • Page 47: Block Diagram Of The Input Scaling, Central Arithmetic Logic, And Multiplication Sections Of The Cpu

    Central Processing Unit Figure 3–1. Block Diagram of the Input Scaling, Central Arithmetic Logic, and Multiplication Sections of the CPU Data write bus (DWEB) Data read bus (DRDB) Program read bus (PRDB) Input scaling section 16 15 Input shifter (32 bits) Central arithmetic logic section Multiplication...
  • Page 48: Block Diagram Of The Input Scaling Section

    3.1 Input Scaling Section A 32-bit input data-scaling shifter (input shifter) aligns a 16-bit value coming from memory to the 32-bit CALU. This data alignment is necessary for data- scaling arithmetic as well as aligning masks for logical operations. The input shifter operates as part of the data path between program or data space and the CALU and, thus, requires no cycle overhead.
  • Page 49: Operation Of The Input Shifter For Sxm

    Input Scaling Section Shift count. The shifter can left-shift a 16-bit value by 0 to 16 bits. The size of the shift (or the shift count) is obtained from one of two sources: A constant embedded in the instruction word. Putting the shift count in the instruction word allows you to use specific data-scaling or alignment op- erations customized for your program code.
  • Page 50: Multiplier

    3.2 Multiplication Section The ’C2xx uses a 16-bit 16-bit hardware multiplier that can produce a signed or unsigned 32-bit product in a single machine cycle. As shown in Figure 3–5, the multiplication section consists of: The 16-bit temporary register (TREG), which holds one of the multipli- cands The multiplier, which multiplies the TREG value by a second value from data memory or program memory...
  • Page 51: Product-Scaling Shifter

    Multiplication Section Inputs. The multiplier accepts two 16-bit inputs: One input is always from the 16-bit temporary register (TREG). The TREG is loaded before the multiplication with a data-value from the data read bus (DRDB). The other input is one of the following: Output.
  • Page 52: Product Shift Modes For The Product-Scaling Shifter

    Table 3–1. Product Shift Modes for the Product-Scaling Shifter † A Q31 number is a binary fraction in which there are 31 digits to the right of the binary point (the base 2 equivalent of the base 10 decimal point). Shift Comments no shift...
  • Page 53: Block Diagram Of The Central Arithmetic Logic Section

    Central Arithmetic Logic Section 3.3 Central Arithmetic Logic Section Figure 3–6 shows the main components of the central arithmetic logic section, which are: The central arithmetic logic unit (CALU), which implements a wide range of arithmetic and logic functions. The 32-bit accumulator (ACC), which receives the output of the CALU and is capable of performing bit shifts on its contents with the help of the carry bit (C).
  • Page 54: Central Arithmetic Logic Unit (Calu)

    3.3.1 Central Arithmetic Logic Unit (CALU) The central arithmetic logic unit (CALU), implements a wide range of arithme- tic and logic functions, most of which execute in a single clock cycle. These functions can be grouped into four categories: 16-bit addition 16-bit subtraction Boolean logic operations Bit testing, shifting, and rotating.
  • Page 55 Central Arithmetic Logic Section Status bits. Four status bits are associated with the accumulator: Carry bit (C). C (bit 9 of status register ST1) is affected during: Overflow mode bit (OVM). OVM (bit 11 of status register ST0) determines how the accumulator will reflect arithmetic overflows. When the processor is in overflow mode (OVM = 1) and an overflow occurs, the accumulator is filled with one of two specific values: Overflow flag bit (OV).
  • Page 56: Output Data-Scaling Shifter

    3.3.3 Output Data-Scaling Shifter The output data-scaling shifter (output shifter) has a 32-bit input connected to the 32-bit output of the accumulator and a 16-bit output connected to the data bus. The shifter copies all 32-bits of the accumulator and then performs a left shift on its content;...
  • Page 57: Auxiliary Register Arithmetic Unit (Arau)

    Auxiliary Register Arithmetic Unit (ARAU) 3.4 Auxiliary Register Arithmetic Unit (ARAU) The CPU also contains the auxiliary register arithmetic unit (ARAU), an arith- metic unit independent of the central arithmetic logic unit (CALU). The main function of the ARAU is to perform arithmetic operations on eight auxiliary reg- isters (AR7 through AR0) in parallel with operations occurring in the CALU.
  • Page 58: Arau And Auxiliary Register Functions

    The eight auxiliary registers (AR7–AR0) provide flexible and powerful indirect addressing. Any location in the 64K data memory space can be accessed us- ing a 16-bit address contained in an auxiliary register. For the details of indirect addressing, see Section 6.3 on page 6-9. To select a specific auxiliary register, load the 3-bit auxiliary register pointer (ARP) of status register ST0 with a value from 0 through 7.
  • Page 59 Auxiliary Register Arithmetic Unit (ARAU) execute phase of the pipeline. For information on the operation of the pipeline, see Section 5.2 on page 5-7. In addition to using the auxiliary registers to reference data-memory address- es, you can use them for other purposes. For example, you can: Use the auxiliary registers to support conditional branches, calls, and re- turns by using the CMPR instruction.
  • Page 60: Status Registers St0 And St1

    3.5 Status Registers ST0 and ST1 The ’C2xx has two status registers, ST0 and ST1, which contain status and control bits. These registers can be stored into and loaded from data memory, thus allowing the status of the machine to be saved and restored for subrou- tines.
  • Page 61: Bit Fields Of Status Registers St0 And St1

    Status Registers ST0 and ST1 Table 3–2. Bit Fields of Status Registers ST0 and ST1 Name Description Auxiliary register pointer buffer. Whenever the auxiliary register pointer (ARP) is loaded, the pre- vious ARP value is copied to the ARB, except during an LST (load status register) instruction. When the ARB is loaded by an LST instruction, the same value is also copied to the ARP.
  • Page 62 Table 3–2. Bit Fields of Status Registers ST0 and ST1 (Continued) Name Description Overflow mode bit. OVM determines how overflows in the CALU are handled. The SETC and CLRC instructions set and clear this bit, respectively. An LST instruction can also be used to modify OVM.
  • Page 63 Memory and I/O Spaces This chapter describes the ’C2xx memory configuration options and the ad- dress maps of the individual ’C2xx devices. It also illustrates typical ways of interfacing the ’C2xx with external memory and external input/output (I/O) devices. Each ’C2xx device has a 16-bit address line that accesses four individually se- lectable spaces (224K words total): A 64K-word program space A 64K-word local data space...
  • Page 64: Overview Of The Memory And I/O Spaces

    Overview of the Memory and I/O Spaces 4.1 Overview of the Memory and I/O Spaces The ’C2xx address map is organized into four individually selectable spaces: Program memory (64K words) contains the instructions to be executed, as well as data used during program execution. Local data memory (64K words) holds data used by the instructions.
  • Page 65: Pins For Interfacing To External Memory And I/O Spaces

    4.1.1 Pins for Interfacing to External Memory and I/O Spaces The pins for interfacing to external memory and I/O space, described in Table 4–1, are of four main types: External buses. Sixteen signals (A15–A0) are available for passing an address from the ’C2xx to another device. Sixteen signals (D15–D0) are available for transferring a data value between the ’C2xx and another de- vice.
  • Page 66: Signals

    Overview of the Memory and I/O Spaces Table 4–1. Pins for Interfacing With External Memory and I/O Spaces (Continued) Pin(s) Read/write signals Request/control BOOT signals MP/MC RAMEN READY HOLD HOLDA Description Read/write pin. This pin indicates the direction of transfer between the ’C2xx and external program, data, or I/O space.
  • Page 67: Program Memory

    4.2 Program Memory Program-memory space holds the code for applications; it can also hold table information and constant operands. The program-memory space addresses up to 64K 16-bit words. Every ’C2xx device contains a DARAM block B0 that can be configured as program memory or data memory. Other on-chip pro- gram memory may be SARAM and ROM or flash memory.
  • Page 68: Interface With External Program Memory

    Program Memory Figure 4–1. Interface With External Program Memory ’C2xx DSP 8 RAM 8 RAM...
  • Page 69: Pages Of Data Memory

    4.3 Local Data Memory The local data-memory space addresses up to 64K 16-bit words. Every ’C2xx device has three on-chip DARAM blocks: B0, B1, and B2. Block B0 has 256 words that are configurable as either data locations or program locations. Blocks B1 (256 words) and B2 (32 words) have a total of 288 words that are available for data memory only.
  • Page 70: Data Page 0 Address Map

    Local Data Memory 4.3.1 Data Page 0 Address Map Table 4–2 shows the address map of data page 0 (addresses 0000h–007Fh). Note the following: Three memory-mapped registers can be accessed with zero wait states: The test/emulation reserved area is used by the test and emulation sys- tems for special information transfers.
  • Page 71: Interfacing With External Local Data Memory

    4.3.2 Interfacing With External Local Data Memory While the ’C2xx is accessing the on-chip local data-memory blocks, the exter- nal memory signals DS and STRB are in high impedance. The external buses are active only when the ’C2xx is accessing locations within the address ranges mapped to external memory.
  • Page 72: Interface With External Local Data Memory

    Local Data Memory Figure 4–3. Interface With External Local Data Memory 4-10 ’C2xx DSP 8 RAM 8 RAM...
  • Page 73: Global Data Memory Configurations

    4.4 Global Data Memory Addresses in the upper 32K words (8000h–FFFFh) of local data memory can be used for global data memory. The global memory allocation register (GREG) determines the size of the global data-memory space, which is be- tween 256 and 32K words. The GREG is connected to the eight LSBs of the internal data bus and is memory-mapped to data-memory location 0005h.
  • Page 74: Interfacing With External Global Data Memory

    Global Data Memory As an example of configuring global memory, suppose you want to designate 8K addresses as global addresses. You would write the 8-bit value 11100000 to the eight LSBs of the GREG (see Figure 4–4). This would designate ad- dresses E000h–FFFFh of data memory as global data addresses (see Figure 4–5).
  • Page 75: Using 8000H-Ffffh For Local And Global External Memory

    toggled between local memory and global memory. For example, in the system of Figure 4–6, when GREG = XXXXXXXX00000000 local data RAM is fully accessible; when GREG = XXXXXXXX10000000 global memory), the local data RAM is not accessible. Figure 4–6. Using 8000h–FFFFh for Local and Global External Memory ’C2xx A15 –...
  • Page 76: Simplified Block Diagram Of Boot Loader Operation

    Boot Loader 4.5 Boot Loader This section applies to ’C2xx devices that have an on-chip boot loader. The boot loader is used for booting software from an 8-bit external ROM to a 16-bit external RAM at reset (see Figure 4–7). The source for your program is an ex- ternal ROM located in external global data memory.
  • Page 77: Connecting The Eprom To The Processor

    4.5.2 Connecting the EPROM to the Processor To map the EPROM into the global data space at address 8000h, make the following connections between the processor and the EPROM (refer to Figure 4–8): Connect the address lines of the processor and the EPROM (see lines A14–A0 in the figure).
  • Page 78: Programming The Eprom

    Boot Loader 4.5.3 Programming the EPROM Texas Instruments fixed-point development tools provide the utilities to gener- ate the boot ROM code. (For an introduction to the procedure for generating boot loader code, see Appendix C, Program Examples .) However, should you need to do the programming, use the following procedure.
  • Page 79: Enabling The Boot Loader

    Figure 4–9 shows how to store a 16-bit program into the 8-bit EPROM. A sub- script h (for example, on Word1 example, on Word1 Figure 4–9. Storing the Program in the EPROM 16-Bit Program Word1 Word2 Wordn 4.5.4 Enabling the Boot Loader To enable the boot loader, tie the BOOT pin low and reset the device.
  • Page 80: Boot Loader Execution

    Boot Loader 4.5.5 Boot Loader Execution Once the EPROM has been programmed and installed, and the boot loader has been enabled, the processor automatically boots the program from EPROM at startup. If you need to reboot the processor during operation, bring the RS pin low to cause a hardware reset.
  • Page 81: Program Code Transferred From 8-Bit Eprom To 16-Bit Ram

    Figure 4–10. Program Code Transferred From 8-Bit EPROM to 16-Bit RAM 8-Bit EPROM Address 8000h Destination = 00h 8001h Destination = 00h 8002h Length N 8003h Length N 8004h Word1 8005h Word1 8006h Word2 8007h Word2 nnnEh Wordn nnnFh Wordn The ’C2xx fetches its interrupt vectors from program-memory locations 0000h–003Fh (the reset vector is fetched from 0000h).
  • Page 82: Interrupt Vectors Transferred First During Boot Load

    Boot Loader Figure 4–11.Interrupt Vectors Transferred First During Boot Load 8-bit EPROM in global data memory Destination (00) 8000h 8001h Destination (00) Length N 8002h 8003h Length N 8004h Interrupt vectors 8083h 8084h Program code nnnFh 4-20 16-bit RAM in program memory 0000h Interrupt vectors 003Fh...
  • Page 83: Boot Loader Program

    4.5.6 Boot Loader Program ********************************************************************************* TMS320C2xx Boot Loader Program This code sets up and executes boot loader code that loads program code from location 8000h in external global data space and transfers it to the destination address specified by the first word read from locations 8000h and 8001h.
  • Page 84 Boot Loader Transfer code LOOP LACC *+,8 SACL HBYTE LACL *+,AR0 #0FFH HBYTE SACL CODEWORD LACL DEST TBLW CODEWORD SACL DEST BANZ LOOP,AR1 SPLK #0,GREG INTR .END Note: The INTR instruction in the boot loader program causes the processor to push a return address onto the stack, but the device does not use a RET to return to this address.
  • Page 85: I/O Address Map For The 'C2Xx

    4.6 I/O Space The ’C2xx supports an I/O address range of 64K 16-bit words. Figure 4–12 shows the ’C2xx I/O address map. Figure 4–12. I/O Address Map for the ’C2xx ’C2xx I/O 0000h External FEFFh FF00h Reserved for test/emulation FF0Fh FF10h I/O-mapped registers and...
  • Page 86: On-Chip Registers Mapped To I/O Space

    I/O Space The map has three main sections of addresses: Addresses 0000h–FEFFh allow access to off-chip peripherals typically used in DSP applications, such as digital-to-analog and analog-to-digital converters. Addresses FF00h–FF0Fh are mapped to on-chip I/O space. These ad- dresses are reserved for test purposes and should not be used. Addresses FF10h–FFFFh are also mapped to on-chip I/O space.
  • Page 87: Accessing I/O Space

    I/O Space 4.6.1 Accessing I/O Space All I/O words (external I/O ports and on-chip I/O registers) are accessed with the IN and OUT instructions. Accesses to external parallel I/O ports are multi- plexed over the same address and data buses for program and data-memory accesses.
  • Page 88: I/O Port Interface Circuitry

    I/O Space Figure 4–13. I/O Port Interface Circuitry 4-26 ’C2xx DSP I/O port address decoder at I/O address 0001h Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 74AC138 Input bit 0 Input bit 1 Input bit 2 Input bit 3 Input bit 4...
  • Page 89: Direct Memory Access Using The Hold Operation

    4.7 Direct Memory Access Using the HOLD Operation The ’C2xx HOLD operation allows direct-memory access to external program, data, and I/O spaces. The process is controlled by two signals: HOLD. An external device can drive the HOLD/INT1 pin low to request control over the external buses.
  • Page 90: An Interrupt Service Routine Supporting Int1 And Hold

    Direct Memory Access Using the HOLD Operation Example 4–1. An Interrupt Service Routine Supporting INT1 and HOLD .mmregs .set 0FFECh ICRSHDW .set 060h Interrupt vectors reset main Int1h int1_hold .space 40*16 main: SPLK #0001h,imr CLRC INTM wait: wait *********Interrupt service routine for HOLD logic***************************** int1_hold: ;...
  • Page 91: Hold During Reset

    Here are three valid methods for exiting the IDLE state, thus deasserting HOLDA and restoring the buses to normal operation: Cause a rising edge on the HOLD/INT1 pin when MODE = 0. Assert system reset at the reset pin. Assert the nonmaskable interrupt NMI at the NMI pin. If reset or NMI occurs while HOLDA is asserted, the CPU will deassert HOLDA regardless of the level on the HOLD/INT1 pin.
  • Page 92: Reset Deasserted Before Hold Deasserted

    Direct Memory Access Using the HOLD Operation Direct Memory Access Using the HOLD Operation Figure 4–15. Reset Deasserted Before HOLD Deasserted 4-30 HOLD HOLDA...
  • Page 93: Device-Specific Information

    4.8 Device-Specific Information For ’C2xx devices other than the ’C209, this section mentions the presence or absence of the boot loader and HOLD features, shows address maps, and explains the contents and configuration of the program-memory and data- memory maps. For details about the memory and I/O spaces of the ’C209, see Section 11.2 on page 11-5.
  • Page 94: C203 Address Map

    Device-Specific Information Figure 4–16. ’C203 Address Map ’C203 Program 0000h Interrupts (external) 003Fh External FDFFh FE00h Reserved (CNF = 1); External (CNF = 0) FEFFh FF00h On-chip DARAM † (CNF = 1); External (CNF = 0) FFFFh † When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space.
  • Page 95: C203 Program-Memory Configuration Options

    DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped to program space or data space, depending on the value of the CNF bit (bit 12 of status register ST1): CNF = 0. B0 is mapped to data space and is accessible at data addresses 0200h–02FFh.
  • Page 96: Tms320C204 Address Maps And Memory Configuration

    Device-Specific Information Table 4–6. ’C203 Data-Memory Configuration Options 4.8.2 TMS320C204 Address Maps and Memory Configuration The ’C204 does not have an on-chip boot loader, but it does support the ’C2xx HOLD operation. Figure 4–16 shows the ’C204 address map. The on-chip program and data memory available on the ’C204 consists of: ROM (4K words, for program memory) DARAM B0 (256 words, for program or data memory)
  • Page 97: C204 Address Map

    Figure 4–17. ’C204 Address Map ’C204 Program 0000h Interrupts (on-chip) (MP/MC = 0) Interrupts (external) (MP/MC = 1) 003Fh On-chip ROM (MP/MC = 0) External (MP/MC = 1) 1000h 0FFFh External FDFFh FE00h Reserved (CNF = 1); External (CNF = 0) FEFFh FF00h On-chip DARAM...
  • Page 98: Do Not Write To Reserved Addresses

    Device-Specific Information You select or deselect the ROM by changing the level on the MP/MC pin at re- set: MP/MC = 0 at reset. The device is configured as a microcomputer. The on-chip ROM is enabled and is accessible at addresses 0000h–0FFFh. The device fetches the reset vector from on-chip ROM.
  • Page 99: C204 Program-Memory Configuration Options

    Table 4–7. ’C204 Program-Memory Configuration Options MP/MC 0000–0FFF 0000–0FFF Table 4–8. ’C204 Data-Memory Configuration Options DARAM B0 (hex) (hex) – FF00–FFFF – – – FF00–FFFF DARAM B0 DARAM B1 (hex) (hex) 0200–02FF 0300–03FF – 0300–03FF Device-Specific Information External Reserved (hex) (hex) 1000–FFFF 1000–FDFF...
  • Page 100: Program Control

    This chapter discusses the processes and features involved in controlling the flow of a program on the ’C2xx. Program control involves controlling the order in which one or more blocks of instructions are executed. Normally, the flow of a program is sequential: the ’C2xx executes instructions at consecutive program-memory addresses.
  • Page 101: Program-Address Generation Block Diagram

    Program-Address Generation 5.1 Program-Address Generation Program flow requires the processor to generate the next program address (sequential or nonsequential) while executing the current instruction. Pro- gram-address generation is illustrated in Figure 5–1 and summarized in Table 5–1. Figure 5–1. Program-Address Generation Block Diagram Next program address Program counter Program address...
  • Page 102: Program Counter (Pc)

    Table 5–1. Program-Address Generation Summary Operation Sequential operation Dummy cycle Return from subroutine Return from table move or block move Branch or call to address specified in instruction Branch or call to address specified in lower half of the accumulator Branch to interrupt service routine The ’C2xx program-address generation logic uses the following hardware: Program counter (PC).
  • Page 103: Interrupts

    Program-Address Generation The ’C2xx can load the PC in a number of ways, to accommodate sequential and nonsequential program flow. Table 5–2 shows what is loaded to the PC according to the code operation performed. Table 5–2. Address Loading to the Program Counter Code Operation Sequential execution Branch...
  • Page 104: A Push Operation

    PSHD and POPD. These instructions allow you to build a stack in data memory for the nesting of subroutines or interrupts beyond eight levels. The PSHD instruction pushes a data-memory value onto the top of the stack. The POPD instruction pops a value from the top of the stack to data memory.
  • Page 105: Micro Stack (Mstack)

    Program-Address Generation Figure 5–3. A Pop Operation Accumulator or memory 5.1.3 Micro Stack (MSTACK) The program-address generation logic uses the 16-bit-wide, 1-level-deep MSTACK to store a return address before executing certain instructions. These instructions use the program-address generation logic to provide a se- cond address in a two-operand instruction.
  • Page 106 5.2 Pipeline Operation Instruction pipelining consists of a sequence of bus operations that occur dur- ing the execution of an instruction. The ’C2xx pipeline has four independent stages: instruction-fetch, instruction-decode, operand-fetch, and instruction- execute. Because the four stages are independent, these operations can overlap.
  • Page 107: Branches, Calls, And Returns

    Branches, Calls, and Returns 5.3 Branches, Calls, and Returns Branches, calls, and returns break the sequential flow of instructions by trans- ferring control to another location in program memory. A branch only transfers control to the new location. A call also saves the return address (the address of the instruction following the call) to the top of the hardware stack.
  • Page 108: Unconditional Returns

    Branches, Calls, and Returns By the time the unconditional call instruction reaches the execute phase of the pipeline, the next two instruction words have already been fetched. These two instruction words are flushed from the pipeline so that they are not executed, the return address is stored to the stack, and then execution continues at the beginning of the called function.
  • Page 109: Conditional Branches, Calls, And Returns

    Conditional Branches, Calls, and Returns 5.4 Conditional Branches, Calls, and Returns The ’C2xx provides branch, call, and return instructions that will execute only if one or more conditions are met. You specify the conditions as operands of the conditional instruction. Table 5–3 lists the conditions that you can use with these instructions and their corresponding operand symbols.
  • Page 110: Stabilization Of Conditions

    Group 2. You can select up to three conditions. Each of these conditions must be from a different category (A, B, or C); you cannot have two condi- tions from the same category. For example, you can test TC, C, and BIO at the same time, but you cannot test C and NC at the same time.
  • Page 111: Conditional Calls

    Conditional Branches, Calls, and Returns The conditional branch instructions are BCND (branch conditionally) and BANZ (branch if currently selected auxiliary register is not equal to 0). The BANZ instruction is useful for implementing loops. 5.4.4 Conditional Calls The conditional call (CC) instruction is executed only when the specified condi- tion or conditions are met (see Table 5–3 on page 5-10).
  • Page 112 Conditional Branches, Calls, and Returns RETC, like RET, is a single-word instruction. However, because of the poten- tial PC discontinuity, it operates with the same effective execution time as the conditional branch (BCND) and the conditional call (CC). By the time the condi- tions of the conditional return instruction have been tested, the two instruction words following the return instruction have already been fetched in the pipe- line.
  • Page 113: Repeating A Single Instruction

    Repeating a Single Instruction 5.5 Repeating a Single Instruction The ’C2xx repeat (RPT) instruction allows the execution of a single instruction N + 1 times, where N is specified as an operand of the RPT instruction. When RPT is executed, the repeat counter (RPTC) is loaded with N. RPTC is then decremented every time the repeated instruction is executed, until RPTC equals zero.
  • Page 114: Interrupts

    5.6 Interrupts Interrupts are hardware- or software-driven signals that cause the ’C2xx to suspend its current program sequence and execute a subroutine. Typically, in- terrupts are generated by hardware devices that need to give data to or take data from the ’C2xx (for example, A/D and D/A converters and other proces- sors).
  • Page 115: Interrupt Table

    Interrupts 3) Execute the interrupt service routine. Once the interrupt is acknowl- edged, the ’C2xx branches to its corresponding subroutine called an inter- rupt service routine (ISR). The ’C2xx follows the branch instruction you place at a predetermined address (the vector location) and executes the ISR you have written.
  • Page 116 Table 5–5. ’C2xx Interrupt Locations and Priorities (Continued) † Note: † The K value is the operand used in an INTR instruction that branches to the corresponding interrupt vector location. ‡ INT2 and INT3 have separate pins but are tied to the same vector location. Vector Name Priority...
  • Page 117: Maskable Interrupts

    Interrupts 5.6.3 Maskable Interrupts When a maskable interrupt is successfully requested by a hardware device or by an external pin, the corresponding flag or flags are activated. These flags are activated whether or not the interrupt is later acknowledged by the proces- sor.
  • Page 118 After an interrupt request is received by the CPU, the CPU must decide wheth- er to acknowledge the request. Maskable hardware interrupts are acknowl- edged only after certain conditions are met: Priority is highest. When more than one hardware interrupt is requested at the same time, the ’C2xx services them according to a set priority rank- ing in which 1 indicates the highest priority.
  • Page 119: Interrupt Flag Register (Ifr)

    Interrupts Figure 5–6 summarizes how maskable interrupts are handled by the CPU. Figure 5–6. Maskable Interrupt Operation Flow Chart 5.6.4 Interrupt Flag Register (IFR) The 16-bit interrupt flag register (IFR), located at address 0006h in data memory space, contains flag bits for all the maskable interrupts. When a mask- able interrupt request reaches the CPU, the corresponding flag is set to 1 in the IFR.
  • Page 120: C2Xx Interrupt Flag Register (Ifr) - Data-Memory Address 0006H

    1 to the corresponding IFR bit. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. Acknowledgement of a hardware request also clears the corresponding IFR bit. A device reset clears all IFR bits. Notes: 1) When an interrupt is requested by an INTR instruction, if the correspond- 2) To avoid double interrupts from the synchronous serial port and the...
  • Page 121: Interrupt Mask Register (Imr)

    Interrupts Bit 3 RINT — Receive interrupt flag. Bit 3 is tied to the receive interrupt for the synchro- nous serial port. To avoid double interrupts, write a 1 to this bit in the interrupt service routine. RINT = 0 RINT = 1 Bit 2 TINT —...
  • Page 122: C2Xx Interrupt Mask Register (Imr) - Data-Memory Address 0004H

    For ’C2xx devices other than the ’C209, Figure 5–8 shows the IMR. Descrip- tions of the bits follow the figure. For a description of the ’C209 IMR, see sub- section 11.3.1, ’C209 Interrupt Registers , on page 11-11. Figure 5–8. ’C2xx Interrupt Mask Register (IMR) — Data-Memory Address 0004h É...
  • Page 123: Interrupt Control Register (Icr)

    Interrupts Bit 0 HOLD/INT1 — HOLD/Interrupt 1 mask. This bit masks or unmasks interrupts re- quested at the HOLD/INT1 pin. HOLD/INT1 = 0 HOLD/INT1 is masked. HOLD/INT1 = 1 HOLD/INT1 is unmasked. 5.6.6 Interrupt Control Register (ICR) The 16-bit interrupt control register (ICR), located at address FFECh in I/O space, controls the function of the HOLD/INT1 pin and individually controls the interrupts INT2 and INT3.
  • Page 124 to mask INT3 (prevent the setting of flags FINT3 and INT2/INT3) write a 0 to MINT3. If INT2/INT3 is not set, the CPU has not received and will not acknowl- edge the interrupt request. When INT2/INT3 is set, one or both of the interrupts is pending. To differentiate the occurrences of the two interrupts, your interrupt service routine can test FINT2 and FINT3 and then branch to the appropriate subroutine.
  • Page 125: C2Xx Interrupt Control Register (Icr) - I/O-Space Address Ffech

    Interrupts Figure 5–9 shows the ICR, and bit descriptions follow the figure. Figure 5–9. ’C2xx Interrupt Control Register (ICR) — I/O-Space Address FFECh É É É É É É É É É É É É É Reserved É É É É É É É É É É É É É Note: 0 = Always read as zeros;...
  • Page 126: Nonmaskable Interrupts

    Bit 0 MINT2 — Interrupt 2 mask. This bit masks the external interrupt INT2 or, in conjunc- tion with the INT2/INT3 bit of the IMR, unmasks INT2. MINT2 = 0 MINT2 = 1 5.6.7 Nonmaskable Interrupts Hardware nonmaskable interrupts can be requested through two pins: RS (reset).
  • Page 127 Interrupts Note: The INTR instruction does not affect IFR flags. When you use the INTR instruction to initiate an interrupt that has an associated flag bit in the IFR, the instruction neither sets nor clears the flag bit. No software write operation can set the IFR flag bits;...
  • Page 128: Interrupt Service Routines (Isrs)

    Figure 5–10. Nonmaskable Interrupt Operation Flow Chart 5.6.8 Interrupt Service Routines (ISRs) After an interrupt has been requested and acknowledged, the CPU follows an interrupt vector to the ISR. The ISR is the program code that actually performs the tasks requested by the interrupt. While performing these tasks, the ISR may also be: Saving and restoring register values Managing ISRs within ISRs...
  • Page 129: Interrupt Latency

    Interrupts Managing ISRs within ISRs The ’C2xx hardware stack allows you to have ISRs within ISRs. When consid- ering nesting ISRs like this, keep the following in mind: If you want the ISR be interrupted by a maskable interrupt, the ISR must unmask the interrupt by setting the appropriate IMR bit (and ICR bit, if ap- plicable) and executing the enable-interrupts instruction (CLRC INTM).
  • Page 130 For an external, maskable hardware interrupt, a minimum latency of eight cycles is required to synchronize the interrupt externally, recognize the inter- rupt, and branch to the interrupt vector location. On the ninth cycle, the inter- rupt vector is fetched. For a software interrupt, the minimum latency consists of four cycles needed to branch to the interrupt vector location.
  • Page 131 Interrupts before the return, the new return address would be added to the hardware stack, even if the stack were already full. To allow the CPU to complete the return, interrupts are also blocked after a RET instruction until at least one instruction at the return address is executed. 5-32...
  • Page 132: Reset Operation

    5.7 Reset Operation Reset (RS) is a nonmaskable external interrupt that can be used at any time to put the ’C2xx into a known state. Reset is the highest priority interrupt; no other interrupt takes precedence over reset. Reset is typically applied after power up when the machine is in an unknown state.
  • Page 133 Reset Operation Peripherals: No other registers or status bits (such as the accumulator, DP, ARP, and the auxiliary registers) are initialized. Table 5–6 and Table 5–7 list the reset values for all the registers mapped to on-chip addresses. 5-34 The timer count is set to its maximum value (FFFFh), the timer divide- down value is set to 0, and the timer starts counting down.
  • Page 134: Reset Values Of On-Chip Registers Mapped To Data Space

    Table 5–6. Reset Values of On-Chip Registers Mapped to Data Space Name Data-Memory Address 0004h GREG 0005h 0006h Table 5–7. Reset Values of On-Chip Registers Mapped to I/O Space I/O Address Name ’C209 Other ’C2xx – FFE8h – FFECh SDTR –...
  • Page 135: Power-Down Mode

    Power-Down Mode 5.8 Power-Down Mode The ’C2xx has a power-down mode that allows the ’C2xx core to enter a dor- mant state and use less power than during normal operation. Executing an IDLE instruction initiates power-down mode. When the IDLE instruction executes, the program counter is incremented once, and then all CPU activi- ties are halted.
  • Page 136: Termination Of Power-Down During A Hold Operation

    5.8.2 Termination of Power-Down During a HOLD Operation One of the necessary steps in the HOLD operation is the execution of an IDLE instruction (see Section 4.7, Direct Memory Access Using The HOLD Opera- tion , on page 4-27) . There are unique characteristics of the HOLD operation that affect how the IDLE state can be exited.
  • Page 137: Addressing Modes

    This chapter explains the three basic memory addressing modes used by the ’C2xx instruction set. The three modes are: Immediate addressing mode Direct addressing mode Indirect addressing mode In immediate addressing, a constant to be manipulated by the instruction is supplied directly as an operand of that instruction.
  • Page 138: Immediate Addressing Mode

    Immediate Addressing Mode 6.1 Immediate Addressing Mode In immediate addressing, the instruction word contains a constant to be ma- nipulated by the instruction. The ’C2xx supports two types of immediate ad- dressing: Short-immediate addressing. Instructions that use short-immediate ad- dressing take an 8-bit, 9-bit, or 13-bit constant as an operand. Short-im- mediate instructions require a single instruction word, with the constant embedded in that word.
  • Page 139: Two Words Loaded Consecutively To The Instruction Register In Example

    Figure 6–2. Two Words Loaded Consecutively to the Instruction Register in Example 6–2 First instruction word: Second instruction word: ADD opcode for long-immediate addressing 16-bit constant = 16 384 = 4000h Immediate Addressing Mode shift = 2 Addressing Modes...
  • Page 140: Direct Addressing Mode

    Direct Addressing Mode 6.2 Direct Addressing Mode In the direct addressing mode, data memory is addressed in blocks of 128 words called data pages. The entire 64K of data memory consists of 512 data pages labeled 0 through 511, as shown in Figure 6–3. The current data page is determined by the value in the 9-bit data page pointer (DP) in status register ST0.
  • Page 141: Instruction Register (Ir) Contents In Direct Addressing Mode

    Figure 6–4. Instruction Register (IR) Contents in Direct Addressing Mode 8 MSBs 7 LSBs To form a complete 16-bit address, the processor concatenates the DP value and the seven LSBs of the instruction register, as shown in Figure 6–5. The DP supplies the nine most significant bits (MSBs) of the address (the page number), and the seven LSBs of the instruction register supply the seven LSBs of the address (the offset).
  • Page 142: Using Direct Addressing Mode

    Direct Addressing Mode 6.2.1 Using Direct Addressing Mode When you use direct addressing mode, the processor uses the DP to find the data page and uses the seven LSBs of the instruction register to find a particu- lar address on that page. Always do the following: 1) Set the data page.
  • Page 143: Using Direct Addressing With Add (Shift Of 16)

    Example 6–3. Using Direct Addressing with ADD (Shift of 0 to 15) LDP #4 ADD 9h,5 ;The contents of data address 0209h are 0 0 0 0 0 0 1 0 0 In Example 6–4, the ADD instruction references a data memory address that is generated as shown following the program code.
  • Page 144: Using Direct Addressing With Addc

    Direct Addressing Mode In Example 6–5, the ADDC instruction references a data memory address that is generated as shown following the program code. Note that if an instruction does not perform shifts, like the ADDC instruction does not, all eight MSBs of the instruction contain the opcode for the instruction type.
  • Page 145: Indirect Addressing Mode

    6.3 Indirect Addressing Mode Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect ad- dressing. Any location in the 64K data memory space can be accessed using a 16-bit address contained in an auxiliary register. 6.3.1 Current Auxiliary Register To select a specific auxiliary register, load the 3-bit auxiliary register pointer (ARP) of status register ST0 with a value from 0 to 7.
  • Page 146: Indirect Addressing Operands

    Indirect Addressing Mode ister as the data memory address and then increments or decrements the content of the current auxiliary register by the index amount. Increment or decrement by an index amount using reverse carry. The value in AR0 is the index amount. After the instruction uses the content of the current auxiliary register as the data-memory address, that content is incremented or decremented by the index amount.
  • Page 147: Next Auxiliary Register

    Table 6–1. Indirect Addressing Operands (Continued) Option Increment by index amount, adding with reverse carry Decrement by index amount, subtracting with reverse carry All increments or decrements are performed by the auxiliary register arithmetic unit (ARAU) in the same cycle during which the instruction is being decoded in the pipeline.
  • Page 148: Indirect Addressing Opcode Format

    Indirect Addressing Mode Example 6–6. Selecting a New Current Auxiliary Register MAR*,AR1 LT *+,AR2 MPY* 6.3.4 Indirect Addressing Opcode Format Figure 6–6 shows the format of the instruction word loaded into the instruction register when you use indirect addressing. The opcode fields are described following the figure.
  • Page 149: Effects Of The Aru Code On The Current Auxiliary Register

    Table 6–2. Effects of the ARU Code on the Current Auxiliary Register ARU Code Table 6–3 shows the opcode field bits and the notation used for indirect ad- dressing. It also shows the corresponding operations performed on the current auxiliary register and the ARP. Arithmetic Operation Performed on Current AR No operation on current AR current AR –...
  • Page 150: Field Bits And Notation For Indirect Addressing

    Indirect Addressing Mode Table 6–3. Field Bits and Notation for Indirect Addressing Instruction Opcode Bits – 8 7 6 5 4 3 2 1 0 8 MSBs 1 0 0 0 0 8 MSBs 1 0 0 0 1 8 MSBs 1 0 0 1 0 8 MSBs 1 0 0 1 1...
  • Page 151: Examples Of Indirect Addressing

    6.3.5 Examples of Indirect Addressing In Example 6–7, when the ADD instruction is fetched from program memory, the instruction register is loaded with the value shown. Example 6–7. No Increment or Decrement ADD *,8 ADD opcode In Example 6–8, when the ADD instruction is fetched from program memory, the instruction register is loaded with the value shown.
  • Page 152: Decrement By 1

    Indirect Addressing Mode Example 6–9. Decrement by 1 ADD *–,8 Example 6–10. Increment by Index Amount ADD *0+,8 Example 6–11. Decrement by Index Amount ADD *0–,8 Example 6–12. Increment by Index Amount With Reverse Carry Propagation ADD *BR0 +,8 ;Operates as in Example 6–10, except that Example 6–13.
  • Page 153: Modifying Auxiliary Register Content

    6.3.6 Modifying Auxiliary Register Content The LAR, ADRK, SBRK, and MAR instructions are specialized instructions for changing the content of an auxiliary register (AR): The LAR instruction loads an AR. The ADRK instruction adds an immediate value to an AR; SBRK subtracts an immediate value.
  • Page 154: Assembly Language Instructions

    Assembly Language Instructions The ’C2xx instruction set supports numerically intensive signal-processing op- erations as well as general-purpose applications such as multiprocessing and high-speed control. The ’C2xx instruction set is compatible with the ’C2x instruction set; code written for the ’C2x can be reassembled to run on the ’C2xx.
  • Page 155: Instruction Set Summary

    Instruction Set Summary 7.1 Instruction Set Summary This section provides a summary of the instruction set in six tables (Table 7–1 to Table 7–6) according to the following functional headings: Accumulator, arithmetic, and logic instructions (see Table 7–1 on page 7-4) Auxiliary register and data page pointer instructions (see Table 7–2 on page 7-7)
  • Page 156 IAAA AAAA (One I followed by seven As) The I at the left represents a bit that reflects whether direct addressing (I = 0) or indirect ad- dressing (I = 1) is being used. When direct addressing is used, the seven As are the seven least significant bits (LSBs) of a data memory address.
  • Page 157: Accumulator, Arithmetic, And Logic Instructions

    Instruction Set Summary ZLVC ZLVC + 1 word Table 7–1. Accumulator, Arithmetic, and Logic Instructions Mnemonic Description Absolute value of ACC Add to ACC with shift of 0 to 15, direct or indirect Add to ACC with shift 0 to 15, long immediate Add to ACC with shift of 16, direct or indirect Add to ACC, short immediate ADDC...
  • Page 158 Table 7–1. Accumulator, Arithmetic, and Logic Instructions (Continued) Mnemonic Description AND ACC with data value, direct or indirect AND with ACC with shift of 0 to 15, long immediate 2 AND with ACC with shift of 16, long immediate CMPL Complement ACC LACC Load ACC with shift of 0 to 15, direct or indirect...
  • Page 159 Instruction Set Summary Table 7–1. Accumulator, Arithmetic, and Logic Instructions (Continued) Mnemonic Description Subtract from ACC with shift of 0 to 15, direct or indirect Subtract from ACC with shift of 0 to 15, long immediate Subtract from ACC with shift of 16, direct or indirect Subtract from ACC, short immediate SUBB...
  • Page 160: Auxiliary Register Instructions

    Table 7–2. Auxiliary Register Instructions Mnemonic Description ADRK Add constant to current AR, short immediate BANZ Branch on current AR not-zero, indirect CMPR Compare current AR with AR0 Load specified AR from specified data location, direct or indirect Load specified AR with constant, short immediate Load specified AR with constant, long immediate...
  • Page 161: Branch Instructions

    Instruction Set Summary Table 7–3. TREG, PREG, and Multiply Instructions (Continued) Mnemonic Description Multiply and accumulate, direct or indirect MACD Multiply and accumulate with data move, direct or indirect Multiply TREG by data value, direct or indirect Multiply TREG by 13-bit constant, short immediate 1 MPYA Multiply and accumulate previous product, direct or indirect...
  • Page 162: Control Instructions

    Table 7–4. Branch Instructions (Continued) Mnemonic Description CALL Call subroutine, indirect Call conditionally INTR Soft interrupt Nonmaskable interrupt Return from subroutine RETC Return conditionally TRAP Software interrupt Table 7–5. Control Instructions Mnemonic Description Test bit, direct or indirect BITT Test bit specified by TREG, direct or indirect CLRC Clear C bit Clear CNF bit...
  • Page 163: I/O And Memory Instructions

    Instruction Set Summary Table 7–5. Control Instructions (Continued) Mnemonic Description POPD Pop top of stack to data memory, direct or indirect 1 PSHD Push data memory value on stack, direct or indirect PUSH Push low ACC onto stack Repeat next instruction, direct or indirect Repeat next instruction, short immediate SETC Set C bit...
  • Page 164 Table 7–6. I/O and Memory Instructions (Continued) Mnemonic Description TBLR Table read, direct or indirect TBLW Table write, direct or indirect Instruction Set Summary Words Cycles Opcode 1010 0110 IAAA AAAA 1010 0111 IAAA AAAA Assembly Language Instructions 7-11...
  • Page 165: How To Use The Instruction Descriptions

    How To Use the Instruction Descriptions 7.2 How To Use the Instruction Descriptions Section 7.3 contains detailed information on the instruction set. The descrip- tion for each instruction presents the following categories of information: Syntax Operands Opcode Execution Status Bits Description Words Cycles...
  • Page 166 Operand x is optional. [, x] Example: For the syntax: ADD dma , [, shift ] you must supply dma , as in the instruction: ADD 7h and you have the option of adding a shift value, as in the instruction: ADD 7h, 5 Operands x1 and x2 are optional, but you cannot include x2 [, x1 [, x2]]...
  • Page 167: Operands

    How To Use the Instruction Descriptions 7.2.2 Operands Operands can be constants, or assembly-time expressions referring to memory, I/O ports, register addresses, pointers, shift counts, and a variety of other constants. The operands category for each instruction description de- fines the variables used for and/or within operands in the syntax expressions. For example, for the ADD instruction, the syntax category gives these syntax expressions: ADD dma [ , shift ]...
  • Page 168: Execution

    The field called dma contains the value dma , which is defined in the operands category. The contents of the fields ARU, N, and NAR are derived from the op- erands ind and n but do not directly correspond to those operands; therefore, a note directs you to the appropriate section for more details.
  • Page 169: Words

    How To Use the Instruction Descriptions 7.2.7 Words The words category specifies the number of memory words (one or two) re- quired to store the instruction. When the number of words depends on the ad- dressing mode used for an instruction, the words category specifies which ad- dressing modes require one word and which require two words.
  • Page 170 If an instruction requires memory operand(s), the rows in the table indicate the location(s) of the operand(s), as defined here: The operand is in internal dual-access RAM. DARAM SARAM The operand is in internal single-access RAM. External The operand is in external memory. For the RPT mode execution, n indicates the number of times a given instruc- tion is repeated by an RPT instruction.
  • Page 171: Examples

    How To Use the Instruction Descriptions The instruction-cycle timings are based on the following assumptions: At least the next four instructions are fetched from the same memory sec- tion (internal or external) that was used to fetch the current instruction (ex- cept in the case of PC discontinuity instructions, such as B, CALL, etc.) In the single-execution mode, there is no pipeline conflict between the cur- rent instruction and the instructions immediately preceding or following...
  • Page 172 The instruction also specifies that AR0 will be the next auxiliary register; therefore, after the instruction ARP = 0. Because no carry is generated during the addition, the carry bit (C) be- comes 0. How To Use the Instruction Descriptions Assembly Language Instructions 7-19...
  • Page 173: Instruction Descriptions

    Instruction Descriptions 7.3 Instruction Descriptions This section contains detailed information on the instruction set for the ’C2xx (For a summary of the instruction set, see Section 7.1.) The instructions are presented alphabetically, and the description for each instruction presents the following categories of information: Syntax Operands...
  • Page 174 Syntax Operands None Opcode Execution Increment PC, then ... |(ACC)| Affected by Status Bits This instruction is not affected by SXM Description If the contents of the accumulator are greater than or equal to zero, the accu- mulator is unchanged by the execution of ABS. If the contents of the accumula- tor are less than zero, the accumulator is replaced by its 2s-complement value.
  • Page 175 Absolute Value of Accumulator Example 1 Example 2 Example 3 Example 4 7-22 Before Instruction 1234h Before Instruction 0FFFFFFFFh ;(OVM = 1) Before Instruction 80000000h ;(OVM = 0) Before Instruction 80000000h After Instruction 1234h After Instruction After Instruction 7FFFFFFFh After Instruction 80000000h...
  • Page 176 Syntax ADD dma [ , shift ] ADD dma , 16 ADD ind [ , shift [ , AR n ] ] ADD ind , 16 [ , AR n ] ADD # k ADD # lk [ , shift ] Operands dma: shift:...
  • Page 177 Add to Accumulator Execution Increment PC, then ... Event (ACC) + ( (data-memory address) (ACC) + ( (data-memory address) (ACC) + k (ACC) + lk Status Bits Affected by SXM and OVM SXM and OVM Description The content of the addressed data memory location or an immediate constant is left-shifted and added to the accumulator.
  • Page 178 Cycles Cycles for a Single ADD Instruction (Using Direct and Indirect Addressing) Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an ADD Instruction (Using Direct Operand DARAM SARAM...
  • Page 179 Add to Accumulator Example 3 Example 4 7-26 ;Add short immediate Before Instruction #1111h,1 ;Add long immediate with shift of 1 Before Instruction After Instruction After Instruction 2224h...
  • Page 180 Syntax ADDC dma ADDC ind [, AR n ] Operands dma: ind: Opcode ADDC dma ADDC ind [, AR n ] Note: Execution Increment PC, then ... (ACC) + (data-memory address) + (C) Affected by Status Bits This instruction is not affected by SXM. Description The contents of the addressed data-memory location and the value of the carry bit are added to the accumulator with sign extension suppressed.
  • Page 181 ADDC Add to Accumulator With Carry Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 ADDC Example 2 ADDC 7-28 Cycles for a Repeat (RPT) Execution of an ADDC Instruction DARAM n+nd n+nd...
  • Page 182 Syntax ADDS dma ADDS ind [, AR n ] Operands dma: ind: Opcode ADDS dma ADDS ind [, AR n ] Note: Execution Increment PC, then ... (ACC) + (data-memory address) Affected by Status Bits This instruction is not affected by SXM. Description The contents of the specified data-memory location are added to the accumu- lator with sign extension suppressed.
  • Page 183 ADDS Add to Accumulator With Sign Extension Suppressed Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 ADDS Example 2 ADDS 7-30 Cycles for a Repeat (RPT) Execution of an ADDS Instruction DARAM n+nd n+nd...
  • Page 184 Syntax ADDT dma ADDT ind [, AR n ] Operands dma: ind: ADDT dma Opcode ADDT ind [, AR n ] Note: Execution Increment PC, then ... (ACC) + [(data-memory address) Affected by Status Bits SXM or OVM Description The data-memory value is left shifted and added to the accumulator, and the result replaces the accumulator contents.
  • Page 185 ADDT Add to Accumulator With Shift Specified by TREG Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 ADDT Example 2 ADDT 7-32 Cycles for a Repeat (RPT) Execution of an ADDT Instruction DARAM n+nd n+nd...
  • Page 186 Syntax ADRK # k Operands ADRK # k Opcode Execution Increment PC, then ... (current AR) + 8-bit positive constant Status Bits None Description The 8-bit immediate value is added, right justified, to the current auxiliary regis- ter (the one specified by the current ARP value) and the result replaces the auxiliary register contents.
  • Page 187 AND With Accumulator Syntax AND dma AND ind [, AR n ] AND # lk [, shift ] AND # lk , 16 Operands dma: shift: ind: AND dma Opcode AND ind [, AR n ] Note: AND # lk [, shift ] AND # lk, 16 Execution Increment PC, then ...
  • Page 188 Status Bits None This instruction is not affected by SXM. Description If direct or indirect addressing is used, the low word of the accumulator is ANDed with a data-memory value, and the result is placed in the low word posi- tion in the accumulator.
  • Page 189 AND With Accumulator Example 1 Example 2 Example 3 7-36 ;(DP = 4: addresses 0200h–027Fh) Before Instruction Data Memory 0210h 00FFh 12345678h Before Instruction 0301h Data Memory 0301h 0FF00h 12345678h #00FFh,4 Before Instruction 12345678h After Instruction Data Memory 0210h 00000078h After Instruction Data Memory 0301h...
  • Page 190: Product Shift Modes

    Syntax APAC Operands None APAC Opcode Execution Increment PC, then ... (ACC) + shifted (PREG) Affected by Status Bits PM and OVM This instruction is not affected by SXM. Description The contents of PREG are shifted as defined by the PM status bits of the ST1 register (see Table 7–7) and added to the contents of the accumulator.
  • Page 191 APAC Add PREG to Accumulator Example APAC 7-38 ;(PM = 01) Before Instruction PREG After Instruction PREG...
  • Page 192 Syntax B pma [, ind [, AR n ] ] Operands pma: ind: B pma [, ind [ , AR n ] ] Opcode Note: Execution Modify (current AR) and (ARP) as specified. Status Bits None Description The current auxiliary register and ARP contents are modified as specified, and control is passed to the designated program-memory address (pma).
  • Page 193 BACC Branch to Location Specified by Accumulator Syntax BACC Operands None Opcode Execution ACC(15:0) Status Bits None Description Control is passed to the 16-bit address residing in the lower half of the accumu- lator. Words Cycles Note: Example BACC The value 191 is loaded into the program counter, and the program continues to execute from that location.
  • Page 194 Syntax BANZ pma [, ind [, AR n ] ] Operands pma: ind: BANZ pma [, ind [ , AR n ] ] Opcode Note: Execution If (current AR) Then pma Else (PC) + 2 Modify (current AR) and (ARP) as specified Status Bits None Description...
  • Page 195 BANZ Branch on Auxiliary Register Not Zero Example 1 BANZ Because the content of AR0 is not zero, the program branches to program ad- dress 0 is loaded into the program counter (PC), and the program continues executing from that location. The default auxiliary register operation is a decre- ment of the current auxiliary register content;...
  • Page 196 Syntax BCND pma , cond 1 [, cond 2] [,...] Operands pma: cond Opcode Note: If cond 1 AND cond 2 AND ... Execution Then pma Else increment PC Status Bits None Description A branch is taken to the specified program-memory address (pma) if the speci- fied conditions are met.
  • Page 197 BCND Branch Conditionally Example BCND If the accumulator contents are less than or equal to zero and the carry bit is set, program address 191 is loaded into the program counter, and the program continues to execute from that location. If these conditions do not hold, execu- tion continues from location PC + 2.
  • Page 198: Bit Numbers And Their Corresponding Bit Codes For Bit Instruction

    Syntax BIT dma , bit code BIT ind , bit code [, AR n ] Operands dma: bit code: ind: BIT dma , bit code Opcode BIT ind , bit code [ ,AR n ] Note: Execution Increment PC, then ... (data bit number (15 –...
  • Page 199 Test Bit Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 7-46 Cycles for a Single BIT Instruction DARAM...
  • Page 200: Bit Numbers And Their Corresponding Bit Codes For Bitt Instruction

    Syntax BITT dma BITT ind [, AR n ] Operands dma: ind: BITT dma Opcode BITT ind [, AR n ] Note: Execution Increment PC, then ... (data bit number (15 –TREG(3:0))) Status Bits Affects Description The BITT instruction copies the specified bit of the data-memory value to the TC bit of status register ST1.
  • Page 201 BITT Test Bit Specified by TREG Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 BITT Example 2...
  • Page 202 Syntax General syntax: BLDD # lk , dma BLDD # lk , ind [, AR n ] BLDD dma , # lk BLDD ind , # lk [, AR n ] Operands dma: ind: BLDD # lk , dma Opcode BLDD # lk , ind [, AR n ] Note: BLDD dma , # lk...
  • Page 203 BLDD Block Move From Data Memory to Data Memory Execution Increment PC, then ... (PC) (source) For indirect, modify (current AR) and (ARP) as specified (PC) + 1 While (repeat counter) (source) For indirect, modify (current AR) and (ARP) as specified (PC) + 1 (repeat counter) –1 (MSTACK)
  • Page 204 Cycles Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM Destination: External Source: SARAM Destination: External Source: External Destination: External † If the destination operand and the code are in the same SARAM block. Block Move From Data Memory to Data Memory Cycles for a Single BLDD Instruction DARAM...
  • Page 205 BLDD Block Move From Data Memory to Data Memory Cycles for a Repeat (RPT) Execution of a BLDD Instruction Operand Source: DARAM Destination: DARAM Source: SARAM Destination: DARAM Source: External n+2+nd Destination: DARAM Source: DARAM Destination: SARAM Source: SARAM ‡ Destination: SARAM Source: External n+2+nd...
  • Page 206 Example 1 BLDD Example 2 BLDD Block Move From Data Memory to Data Memory #300h,20h ;(DP = 6) Before Instruction Data Memory 300h 320h *+,#321h,AR3 Before Instruction 301h Data Memory 301h 321h Assembly Language Instructions After Instruction Data Memory 300h 320h After Instruction Data Memory...
  • Page 207 BLPD Block Move From Program Memory to Data Memory Syntax General syntax: BLPD # pma , dma BLPD # pma , ind [, AR n ] Operands pma: dma: ind: BLPD #pma, dma Opcode BLPD #pma, ind [ , AR n ] Note: Execution Increment PC, then ...
  • Page 208 BLPD Block Move From Program Memory to Data Memory Description A word in program memory pointed to by the source is copied to data-memory space pointed to by destination . The first word of the source space is pointed to by a long-immediate value. The data-memory destination space is pointed to by a data-memory address or auxiliary register pointer.
  • Page 209 BLPD Block Move From Program Memory to Data Memory Cycles Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External...
  • Page 210 Cycles for a Repeat (RPT) Execution of a BLPD Instruction (Continued) Operand Source: SARAM ‡ Destination: SARAM Source: External n+2+np Destination: SARAM Source: DARAM/ROM 2n+2+nd Destination: External Source: SARAM 2n+2+nd Destination: External Source: External 4n+np Destination: External † If the destination operand and the code are in the same SARAM block ‡...
  • Page 211 CALA Call Subroutine at Location Specified by Accumulator Syntax CALA Operands None Opcode Execution PC + 1 ACC(15:0) Status Bits None Description The current program counter (PC) is incremented and pushed onto the top of the stack (TOS). Then, the contents of the lower half of the accumulator are loaded into the PC.
  • Page 212 Syntax CALL pma [, ind [, AR n ] ] Operands pma: ind: CALL pma [ , ind [ , AR n ] ] Opcode Note: Execution PC + 2 Modify (current AR) and (ARP) as specified. Status Bits None Description The current program counter (PC) is incremented and pushed onto the top of the stack (TOS).
  • Page 213 Call Conditionally Syntax CC pma , cond 1 [, cond 2] [,...] Operands pma: cond Opcode Note: Execution If cond 1 AND cond 2 AND ... Then Else Status Bits None Description Control is passed to the specified program-memory address (pma) if the speci- fied conditions are met.
  • Page 214 Call Conditionally Example PGM191,LEQ,C If the accumulator contents are less than or equal to zero and the carry bit is set, 0BFh (191) is loaded into the program counter, and the program continues to execute from that location. If the conditions are not met, execution continues at the instruction following the CC instruction.
  • Page 215 CLRC Clear Control Bit Syntax CLRC control bit Operands control bit: CLRC C Opcode CLRC CNF CLRC INTM CLRC OVM CLRC SXM CLRC TC CLRC XF Execution Increment PC, then ... control bit Status Bits None Description The specified control bit is cleared to 0. Note that the LST instruction can also be used to load ST0 and ST1.
  • Page 216 Words Cycles Example CLRC TC Cycles for a Single CLRC Instruction DARAM SARAM Cycles for a Repeat (RPT) Execution of a CLRC Instruction DARAM SARAM ;(TC is bit 11 of ST1) Before Instruction x9xxh Assembly Language Instructions CLRC Clear Control Bit External External After Instruction...
  • Page 217 CMPL Complement Accumulator Syntax CMPL Operands None Opcode Execution Increment PC, then ... (ACC) Status Bits None Description The contents of the accumulator are replaced with its logical inversion (1s complement). The carry bit is unaffected. Words Cycles Example CMPL 7-64 Cycles for a Single CMPL Instruction DARAM...
  • Page 218 Syntax CMPR CM Operands Opcode Execution Increment PC, then ... Compare (current AR) to (AR0) and place the result in the TC bit of status register ST1. Affects Status Bits This instruction is not affected by SXM. It does not affect SXM. Description The CMPR instruction performs a comparison specified by the value of CM: If CM = 00, test whether (current AR) = (AR0)
  • Page 219 DMOV Data Move in Data Memory Syntax DMOV dma DMOV ind [, AR n ] Operands dma: ind: Opcode DMOV dma DMOV ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) Affected by Status Bits Description The contents of the specified data-memory address are copied into the con- tents of the next higher address.
  • Page 220 Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block ‡ If used on external memory, DMOV reads the specified memory location but performs no operations. Operand DARAM SARAM External † If the operand and the code are in the same SARAM block ‡...
  • Page 221 IDLE Idle Until Interrupt Syntax IDLE Operands None Opcode Execution Increment PC, then wait for unmasked or nonmaskable hardware interrupt. Status Bits Affected by INTM Description The IDLE instruction forces the program being executed to halt until the CPU receives a request from an unmasked hardware interrupt (external or internal), NMI, or reset.
  • Page 222 Syntax IN dma , PA IN ind , PA [, AR n ] Operands dma: ind: IN dma , PA Opcode IN ind ,PA [ , AR n ] Note: Execution Increment PC, then ... Data bus lines D15–D0 (PA) Status Bits None Description...
  • Page 223 Input Data From Port Cycles Operand Destination: DARAM 2+io Destination: SARAM 2+io Destination: External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an IN Instruction Operand Destination: DARAM 2n+nio Destination: SARAM 2n+nio...
  • Page 224 Syntax INTR K Operands Opcode Execution (PC) + 1 corresponding interrupt vector location Status Bits Affects INTM This instruction is not affected by INTM. Description The processor has locations for 32 interrupt vectors; each location is repre- sented by a value K from 0 to 31. The INTR instruction is a software interrupt that transfers program control to the program-memory address specified by K.
  • Page 225 LACC Load Accumulator With Shift Syntax LACC dma [, shift ] LACC dma, 16 LACC ind [, shift [, AR n ] ] LACC ind , 16[, AR n ] LACC # lk [, shift ] Operands dma: shift: ind: LACC dma [ , shift ] Opcode LACC dma , 16...
  • Page 226 Execution Increment PC, then ... Event (data-memory address) (data-memory address) shift Status Bits Affected by Description The contents of the specified data-memory address or a 16-bit constant are left shifted and loaded into the accumulator. During shifting, low-order bits are zero filled.
  • Page 227 LACC Load Accumulator With Shift Example 1 LACC Example 2 LACC Example 3 LACC 7-74 ;(DP = 8: addresses 0400h–047Fh, ;SXM = 0) Before Instruction Data Memory 406h 012345678h ;(SXM = 0) Before Instruction 0300h Data Memory 300h 0FFh 12345678h #0F000h,1 ;(SXM = 1) Before Instruction 012345678h...
  • Page 228 Syntax LACL dma LACL ind [, AR n ] LACL # k Operands dma: ind: Opcode LACL dma LACL ind [, AR n ] Note: LACL # k Execution Increment PC, then ... Events ACC(31:16) (data-memory address) ACC(31:8) ACC(7:0) Status Bits This instruction is not affected by SXM.
  • Page 229 LACL Load Low Accumulator and Clear High Accumulator Cycles Cycles for a Single LACL Instruction (Using Direct and Indirect Addressing) Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an LACL Instruction (Using Direct Operand DARAM SARAM...
  • Page 230 LACL Load Low Accumulator and Clear High Accumulator Example 3 LACL #10h Before Instruction After Instruction 7FFFFFFFh 010h Assembly Language Instructions 7-77...
  • Page 231 LACT Load Accumulator With Shift Specified by TREG Syntax LACT dma LACT ind [, AR n ] Operands dma: ind: Opcode LACT dma LACT ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) If SXM = 1: Then (data-memory address) is sign extended.
  • Page 232 Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 LACT Example 2 LACT Load Accumulator With Shift Specified by TREG Cycles for a Single LACT Instruction...
  • Page 233 Load Auxiliary Register Syntax LAR AR x , dma LAR AR x , ind [, AR n ] LAR AR x , # k LAR AR x , # lk Operands dma: ind: LAR AR x , dma Opcode LAR AR x , ind [ , AR n ] Note: LAR AR x , # k LAR AR x , # lk...
  • Page 234 Description The contents of the specified data-memory address or an 8-bit or 16-bit con- stant are loaded into the specified auxiliary register (ARx). The specified con- stant is acted upon like an unsigned integer, regardless of the value of SXM. The LAR and SAR (store auxiliary register) instructions can be used to load and store the auxiliary registers during subroutine calls and interrupts.
  • Page 235 Load Auxiliary Register Example 1 Example 2 Note: LAR in the indirect addressing mode ignores any AR modifications if the AR specified by the instruction is the same as that pointed to by the ARP. There- fore, in Example 2, AR4 is not decremented after the LAR instruction. Example 3 Example 4 7-82...
  • Page 236 Syntax LDP dma LDP ind [, AR n ] LDP # k Operands dma: ind: LDP dma Opcode LDP ind [, AR n ] Note: LDP # k Execution Increment PC, then ... Event Nine LSBs of (data-memory address) Status Bits Affects Description The nine LSBs of the contents of the addressed data-memory location or a...
  • Page 237 Load Data Page Pointer Cycles for a Single LDP Instruction (Using Direct and Indirect Addressing) Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an LDP Instruction (Using Direct and Operand DARAM SARAM...
  • Page 238 Syntax LPH dma LPH ind [, AR n ] Operands dma: ind: Opcode LPH dma LPH ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) Status Bits None Description The 16 high-order bits of the PREG are loaded with the content of the specified data-memory address.
  • Page 239 Load Product Register High Word Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 7-86 Cycles for a Repeat (RPT) Execution of an LPH Instruction DARAM n+nd n+nd DAT0 ;(DP = 4) Before Instruction...
  • Page 240: Lst #0 Operation

    Syntax LST # m , dma LST # m , ind [, AR n ] Operands dma: ind: Opcode LST #0, dma LST #0, ind [, AR n ] Note: LST #1, dma LST #1, ind [, AR n ] Note: Execution Increment PC, then ...
  • Page 241: Lst #1 Operation

    Load Status Register Figure 7–4. LST #1 Operation Data Status Bits Affects ARB, ARP, OV, OVM, DP, CNF, TC, SXM, C, XF, and PM This instruction does not affect INTM. Description The specified status register (ST0 or ST1) is loaded with the addressed data- memory value.
  • Page 242 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 Example 3 Cycles for a Repeat (RPT) Execution of an LST Instruction DARAM 2n+nd 2n+nd *,AR0 #0,*,AR1 ;The data memory word addressed by the ;contents of auxiliary register AR0 is ;loaded into status register ST0,except ;for the INTM bit.
  • Page 243 Load Status Register Example 4 7-90 #1,00h ;(DP = 6) ;Note that the ARB is loaded with ;the new ARP value. Before Instruction Data Memory 300h E1BCh 0406h 09ECh After Instruction Data Memory 300h E1BCh E406h E1FCh...
  • Page 244 Syntax LT dma LT ind [, AR n ] Operands dma: ind: LT dma Opcode LT ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) Status Bits None Description TREG is loaded with the contents of the specified data-memory address. The LT instruction may be used to load TREG in preparation for multiplication.
  • Page 245 Load TREG Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 7-92 Cycles for a Repeat (RPT) Execution of an LT Instruction DARAM n+nd n+nd ;(DP = 8: addresses 0400h–047Fh) Before Instruction Data Memory 418h...
  • Page 246 Syntax LTA dma LTA ind [, AR n ] Operands dma: ind: LTA dma Opcode LTA ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) (ACC) + shifted (PREG) Status Bits Affected by PM and OVM Description TREG is loaded with the contents of the specified data-memory address.
  • Page 247 Load TREG and Accumulate Previous Product Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Data Memory Example 2 Data Memory 7-94 Cycles for a Repeat (RPT) Execution of an LTA Instruction DARAM n+nd n+nd...
  • Page 248 Syntax LTD dma LTD ind [, AR n ] Operands dma: ind: LTD dma Opcode LTD ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) (data-memory address) (ACC) + shifted (PREG) Affected by Status Bits PM and OVM Description TREG is loaded with the contents of the specified data-memory address.
  • Page 249 Load TREG, Accumulate Previous Product, and Move Data Words Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block ‡ If the LTD instruction is used with external memory, the data move will not occur. (The previous product will be accumulated, and the TREG will be loaded.) Operand DARAM...
  • Page 250 Example 2 Note: Load TREG, Accumulate Previous Product, and Move Data *,AR3 ;(PM = 0) Before Instruction 3FEh Data Memory 3FEh Data Memory 3FFh TREG PREG The data move function for LTD can occur only within on-chip data memory RAM blocks. Assembly Language Instructions After Instruction Data Memory...
  • Page 251 Load TREG and Store PREG in Accumulator Syntax LTP dma LTP ind [, AR n ] Operands dma: ind: Opcode LTP dma LTP ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) shifted (PREG) Affected by Status Bits Description The TREG is loaded with the content of the addressed data-memory location,...
  • Page 252 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 Load TREG and Store PREG in Accumulator Cycles for a Repeat (RPT) Execution of an LTP Instruction DARAM n+nd n+nd ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product)
  • Page 253 Load TREG and Subtract Previous Product Syntax LTS dma LTS ind [, AR n ] Operands dma: ind: Opcode LTS dma LTS ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) ACC – shifted (PREG) Status Bits Affected by PM and OVM Description...
  • Page 254 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 Load TREG and Subtract Previous Product Cycles for a Repeat (RPT) Execution of an LTS Instruction DARAM n+nd n+nd DAT36 ;(DP = 6: addresses 0300h–037Fh, ;PM = 0: no shift of product)
  • Page 255 Multiply and Accumulate Syntax MAC pma , dma MAC pma , ind [, AR n ] Operands dma: pma: ind: MAC pma , dma Opcode MAC pma , ind [, AR n ] Note: Execution Increment PC, then . . . (PC) (ACC) + shifted (PREG) (data-memory address)
  • Page 256 Description The MAC instruction: Adds the previous product, shifted as defined by the PM status bits, to the accumulator. The carry bit is set (C = 1) if the result of the addition gener- ates a carry and is cleared (C = 0) if it does not generate a carry. Loads the TREG with the content of the specified data-memory address.
  • Page 257 Multiply and Accumulate Cycles Operand Operand 1: DARAM/ Operand 2: DARAM Operand 1: SARAM Operand 2: DARAM Operand 1: External Operand 2: DARAM Operand 1: DARAM/ Operand 2: SARAM Operand 1: SARAM † Operand 2: SARAM Operand 1: External Operand 2: SARAM Operand 1: DARAM/ Operand 2: External Operand 1: SARAM...
  • Page 258 Cycles for a Repeat (RPT) Execution of an MAC Instruction (Continued) Operand Operand 1: DARAM/ Operand 2: SARAM Operand 1: SARAM † Operand 2: SARAM 2n+2 Operand 1: External n+2+np Operand 2: SARAM Operand 1: DARAM/ n+2+nd Operand 2: External Operand 1: SARAM n+2+nd Operand 2: External...
  • Page 259 MACD Multiply and Accumulate With Data Move Syntax MACD pma , dma MACD pma , ind [, AR n ] Operands dma: pma: ind: MACD pma, dma Opcode MACD pma, ind [ , AR n ] Note: Execution Increment PC, then . . . (PC) (ACC) + shifted (PREG) (data-memory address)
  • Page 260 Status Bits Affected by PM and OVM Description The MACD instruction: Adds the previous product, shifted as defined by the PM status bits, to the accumulator. The carry bit is set (C = 1) if the result of the addition gener- ates a carry and is cleared (C = 0) if it does not generate a carry.
  • Page 261 MACD Multiply and Accumulate With Data Move Cycles for a Single MACD Instruction (Continued) Operand Operand 1: External Operand 2: DARAM Operand 1: DARAM/ Operand 2: SARAM Operand 1: SARAM Operand 2: SARAM Operand 1: External Operand 2: SARAM Operand 1: DARAM/ §...
  • Page 262 Cycles for a Repeat (RPT) Execution of an MACD Instruction (Continued) Operand Operand 1: SARAM ‡ Operand 2: SARAM Operand 1: External 2n+np Operand 2: SARAM Operand 1: DARAM/ n+2+nd ¶ Operand 2: External Operand 1: SARAM n+2+nd ¶ Operand 2: External Operand 1: External 2n+2+np ¶...
  • Page 263 MACD Multiply and Accumulate With Data Move Example 2 MACD Note: 7-110 0FF00h,*,AR6 Before Instruction 308h Data Memory 308h Data Memory 309h Program Memory FF00h TREG PREG 458972h 723EC41h The data move function for MACD can occur only within on-chip data memory RAM blocks.
  • Page 264 Syntax MAR dma MAR ind [, AR n ] Operands ind: MAR dma Opcode MAR ind [, AR n ] Note: Execution Event(s) Increment PC Increment PC Modify (current AR) and (ARP) as specified Status Bits Affects None ARP and ARB Description In the direct addressing mode, the MAR instruction acts as a NOP instruction.
  • Page 265 Modify Auxiliary Register Words Cycles Example 1 Example 2 7-112 Cycles for a Single MAR Instruction DARAM SARAM Cycles for a Repeat (RPT) Execution of an MAR Instruction DARAM SARAM *,AR1 ;Load the ARP with 1. Before Instruction *+,AR5 ;Increment current auxiliary ;register (AR1) and load ARP ;with 5.
  • Page 266 Syntax MPY dma MPY ind [, AR n ] MPY # k Operands dma: ind: Opcode MPY dma MPY ind [, AR n ] Note: MPY # k Execution Increment PC, then ... Event (TREG) (TREG) Status Bits None Description The contents of TREG are multiplied by the contents of the addressed data memory location.
  • Page 267 Multiply Cycles Cycles for a Single MPY Instruction (Using Direct and Indirect Addressing) Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an MPY Instruction (Using Direct Operand DARAM SARAM...
  • Page 268 Example 2 Example 3 *,AR2 Before Instruction 40Dh Data Memory 40Dh TREG PREG #031h Before Instruction TREG PREG Assembly Language Instructions Multiply After Instruction Data Memory 40Dh TREG PREG After Instruction TREG PREG 40Dh 7-115...
  • Page 269 MPYA Multiply and Accumulate Previous Product Syntax MPYA dma MPYA ind [, AR n ] Operands dma: ind: MPYA dma Opcode MPYA ind [, AR n ] Note: Execution Increment PC, then ... (ACC) + shifted (PREG) (TREG) Status Bits Affected by PM and OVM Description...
  • Page 270 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 MPYA Example 2 MPYA Multiply and Accumulate Previous Product Cycles for a Repeat (RPT) Execution of an MPYA Instruction DARAM n+nd n+nd DAT13 ;(DP = 6, PM = 0)
  • Page 271 MPYS Multiply and Subtract Previous Product Syntax MPYS dma MPYS ind [, AR n ] Operands dma: ind: MPYS dma Opcode MPYS ind [ , AR n ] Note: Execution Increment PC, then ... (ACC) – shifted (PREG) (TREG) Status Bits Affected by PM and OVM Description...
  • Page 272 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 MPYS Example 2 MPYS Multiply and Subtract Previous Product Cycles for a Repeat (RPT) Execution of an MPYS Instruction DARAM n+nd n+nd DAT13 ;(DP = 6, PM = 0)
  • Page 273 MPYU Multiply Unsigned Syntax MPYU dma MPYU ind [, AR n ] Operands dma: ind: Opcode MPYU dma MPYU ind [,AR n ] Note: Execution Increment PC, then ... Unsigned (TREG) Status Bits None This instruction is not affected by SXM. Description The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data-memory location.
  • Page 274 Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 MPYU Example 2 MPYU Cycles for a Single MPYU Instruction DARAM...
  • Page 275 Negate Accumulator Syntax Operands None Opcode Execution Increment PC, then ... (ACC) Status Bits Affected by Description The content of the accumulator is replaced with its arithmetic complement (2s complement). The OV bit is set when taking the NEG of 8000 0000h. If OVM = 1, the accumulator content is replaced with 7FFF FFFFh.
  • Page 276 Example 3 ;(OVM = 1) Before Instruction 080000000h Assembly Language Instructions Negate Accumulator After Instruction 7FFFFFFFh 7-123...
  • Page 277 Nonmaskable Interrupt Syntax Operands None Opcode Execution (PC) + 1 INTM Status Bits Affects INTM This instruction is not affected by INTM. Description The NMI instruction forces the program counter to the nonmaskable interrupt vector located at 24h. This instruction has the same effect as the hardware nonmaskable interrupt NMI.
  • Page 278 Syntax Operands None Opcode Execution Increment PC Status Bits None Description No operation is performed. The NOP instruction affects only the PC. The NOP instruction is useful to create pipeline and execution delays. Words Cycles Example Cycles for a Single NOP Instruction DARAM Cycles for a Repeat (RPT) Execution of an NOP Instruction DARAM...
  • Page 279 NORM Normalize Contents of Accumulator Syntax NORM ind Operands ind: NORM ind Opcode Note: Execution Increment PC, then ... If (ACC) = 0: Then TC Else, if (ACC(31)) XOR (ACC(30)) = 0: Then TC Else TC Affects Status Bits Description The NORM instruction normalizes a signed number that is contained in the ac- cumulator.
  • Page 280 Notes: For the NORM instruction, the auxiliary register operations are executed dur- ing the fourth phase of the pipeline, the execution phase. For other instruc- tions, the auxiliary register operations take place in the second phase of the pipeline, in the decode phase. Therefore: 1) The auxiliary register values should not be modified by the two instruction words following NORM.
  • Page 281 NORM Normalize Contents of Accumulator Example 3 15-Bit Normalization: NORM The method used in Example 2 normalizes a 32-bit number and yields a 5-bit exponent magnitude. The method used in Example 3 normalizes a 16-bit num- ber and yields a 4-bit magnitude. If the number requires only a small amount of normalization, the Example 2 method may be preferable to the Example 3 method because the loop in Example 2 runs only until normalization is com- plete.
  • Page 282 Syntax OR dma OR ind [, AR n ] OR # lk [, shift ] OR # lk, 16 Operands dma: shift: ind: OR dma Opcode OR ind [, AR n ] Note: OR # lk [, shift ] OR # lk [ , 16] Execution Increment PC, then ...
  • Page 283 OR With Accumulator Status Bits None This instruction is not affected by SXM. Description An OR operation is performed on the contents of the accumulator and the con- tents of the addressed data-memory location or a long-immediate value. The long-immediate value may be shifted before the OR operation. The result re- mains in the accumulator.
  • Page 284 Example 1 OR DAT8 Example 2 OR *,AR0 Example 3 OR #08111h,8 ;(DP = 8) Before Instruction Data Memory 408h 0F000h 100002h Before Instruction 300h Data Memory 300h 1111h 222h Before Instruction 0FF0000h Assembly Language Instructions OR With Accumulator After Instruction Data Memory 408h 0F000h...
  • Page 285 Output Data to Port Syntax OUT dma , PA OUT ind , PA [, AR n ] Operands dma: ind: OUT dma , PA Opcode OUT ind , PA [, AR n ] Note: Execution Increment PC, then ... (data-memory address) (data-memory address) Status Bits None...
  • Page 286 Cycles Operand Source: DARAM 3+io Source: SARAM 3+io Source: External † If the operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of an OUT Instruction Operand Destination: DARAM 3n+nio Destination: SARAM 3n+nio Destination: External 5n–2+nd †...
  • Page 287 Load Accumulator With Product Register Syntax Operands None Opcode Execution Increment PC, then ... shifted (PREG) Affected by Status Bits Description The content of PREG, shifted as specified by the PM status bits, is loaded into the accumulator. Words Cycles Example 7-134 Cycles for a Single PAC Instruction...
  • Page 288 Syntax Operands None Opcode Execution Increment PC, then ... (TOS) ACC(31:16) Pop stack one level Status Bits None Description The content of the top of the stack (TOS) is copied to the low accumulator, and then the stack values move up one level. The upper half of the accumulator is set to all zeros.
  • Page 289 Pop Top of Stack to Low Accumulator Example 7-136 Before Instruction Stack After Instruction Stack...
  • Page 290 Syntax POPD dma POPD ind [, AR n ] Operands dma: ind: POPD dma Opcode POPD ind [,AR n ] Note: Execution Increment PC, then ... (TOS) Pop stack one level Status Bits None Description The value from the top of the stack is transferred into the data-memory location specified by the instruction.
  • Page 291 POPD Pop Top of Stack to Data Memory Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 POPD Example 2 POPD 7-138 Cycles for a Repeat (RPT) Execution of a POPD Instruction DARAM 2n+nd 2n+nd...
  • Page 292 Syntax PSHD dma PSHD ind [, AR n ] Operands dma: ind: PSHD dma Opcode PSHD ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) Push all stack locations down one level Status Bits None Description The value from the data-memory location specified by the instruction is trans- ferred to the top of the stack.
  • Page 293 PSHD Push Data-Memory Value Onto Stack Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 PSHD Example 2 PSHD 7-140 Cycles for a Repeat (RPT) Execution of a PSHD Instruction DARAM n+nd n+nd...
  • Page 294 Syntax PUSH Operands None Opcode Execution Increment PC, then... Push all stack locations down one level ACC(15:0) Status Bits None Description The stack values move down one level. Then, the content of the lower half of the accumulator is copied onto the top of the hardware stack. The hardware stack operates as a last-in, first-out stack with eight locations.
  • Page 295 Return From Subroutine Syntax Operands None Opcode Execution (TOS) Pop stack one level. Status Bits None Description The contents of the top stack register are copied into the program counter. The remaining stack values are then copied up one level. RET concludes subrou- tines and interrupt service routines to return program control to the calling or interrupted program sequence.
  • Page 296 Syntax RETC cond 1 [, cond 2] [ ,... ] Operands cond ‡ Opcode Note: Execution If cond 1 AND cond 2 AND ... (TOS) Pop stack one level Else, continue Status Bits None Description If the specified condition or conditions are met, a standard return is executed (see the description for the RET instruction).
  • Page 297 Rotate Accumulator Left Syntax Operands None Opcode Execution Increment PC, then ... ACC(0) (ACC(31)) (ACC(30:0)) Status Bits Affects This instruction is not affected by SXM. Description The ROL instruction rotates the accumulator left one bit. The value of the carry bit is shifted into the LSB, then the MSB is shifted into the carry bit.
  • Page 298 Syntax Operands None Opcode Execution Increment PC, then ... ACC(31) (ACC(0)) (ACC(31:1)) Status Bits Affects This instruction is not affected by SXM. Description The ROR instruction rotates the accumulator right one bit. The value of the carry bit is shifted into the MSB of the accumulator, then the LSB of the accu- mulator is shifted into the carry bit.
  • Page 299 Repeat Next Instruction Syntax RPT dma RPT ind [, AR n ] RPT # k Operands dma: ind: Opcode RPT dma RPT ind [, AR n ] Note: RPT # k Execution Increment PC, then ... Event (data-memory address) RPTC Status Bits None Description...
  • Page 300 Cycles Cycles for a Single RPT Instruction (Using Direct and Indirect Addressing) Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 Example 3 DARAM Cycles for a Single RPT Instruction (Using Short Immediate Addressing) DARAM DAT127...
  • Page 301 SACH Store High Accumulator With Shift Syntax SACH dma [, shift2 ] SACH ind [, shift2 [, AR n ] ] Operands dma: shift2: ind: SACH dma [ , shift2 ] Opcode SACH ind [ , shift 2 [ , AR n ] ] Note: Execution Increment PC, then ...
  • Page 302 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 SACH Example 2 SACH Store High Accumulator With Shift Cycles for a Repeat (RPT) Execution of an SACH Instruction DARAM 2n+nd 2n+nd DAT10,1 ;(DP = 4: addresses 0200h–027Fh,...
  • Page 303 SACL Store Low Accumulator With Shift Syntax SACL dma [, shift2 ] SACL ind [, shift2 [, AR n ] ] Operands dma: shift2: ind: SACL dma [ , shift2 ] Opcode SACL ind [ , shift2 [ , AR n ] ] Note: Execution Increment PC, then ...
  • Page 304 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block. Example 1 SACL Example 2 SACL Store Low Accumulator With Shift Cycles for a Repeat (RPT) Execution of an SACL Instruction DARAM 2n+nd 2n+nd DAT11,1 ;(DP = 4: addresses 0200h–027Fh,...
  • Page 305 Store Auxiliary Register Syntax SAR AR x , dma SAR AR x, ind [, AR n ] Operands dma: ind: SAR AR x , dma Opcode SAR AR x , ind [ , AR n ] Note: Execution Increment PC, then ... (ARx) Status Bits None...
  • Page 306 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 Cycles for a Repeat (RPT) Execution of an SAR Instruction DARAM 2n+nd 2n+nd AR0,DAT30 ;(DP = 6: addresses 0300h–037Fh) Before Instruction Data Memory 31Eh...
  • Page 307 SBRK Subtract Short-Immediate Value From Auxiliary Register Syntax SBRK # k Operands SBRK # k Opcode Execution Increment PC, then ... (current AR) – k Note that k is an 8-bit positive constant. Status Bits None Description The 8-bit immediate value is subtracted, right justified, from the content of the current auxiliary register (the one pointed to by the ARP) and the result re- places the contents of the auxiliary register.
  • Page 308 Syntax SETC control bit Operands control bit: SETC C Opcode SETC CNF SETC INTM SETC OVM SETC SXM SETC TC SETC XF Execution Increment PC, then ... control bit Status Bits None Description The specified control bit is set to 1. Note that LST may also be used to load ST0 and ST1.
  • Page 309 SETC Set Control Bit Words Cycles Example SETC 7-156 Cycles for a Single SETC Instruction DARAM SARAM Cycles for a Repeat (RPT) Execution of an SETC Instruction DARAM SARAM ;TC is bit 11 of ST1 Before Instruction x1xxh External External After Instruction x9xxh...
  • Page 310 Syntax Operands None Opcode Execution Increment PC, then ... (ACC(31)) (ACC(30:0)) ACC(0) Status Bits Affects This instruction is not affected by SXM. Description The SFL instruction shifts the entire accumulator left one bit. The least signifi- cant bit is filled with a 0, and the most significant bit is shifted into the carry bit (C).
  • Page 311 Shift Accumulator Right Syntax Operands None Opcode Execution Increment PC, then ... If SXM = 0 Then 0 If SXM = 1 Then (ACC(31)) (ACC(31:1)) (ACC(0)) Status Bits Affected by Description The SFR instruction shifts the accumulator right one bit. If SXM = 1, the instruction produces an arithmetic right shift.
  • Page 312 Example 1 Example 2 ;(SXM = 0: no sign extension) Before Instruction B0001234h ;(SXM = 1: sign extend) Before Instruction B0001234h Assembly Language Instructions Shift Accumulator Right After Instruction 5800091Ah After Instruction D800091Ah 7-159...
  • Page 313 SPAC Subtract PREG From Accumulator Syntax SPAC Operands None Opcode Execution Increment PC, then ... (ACC) – shifted (PREG) Affected by Status Bits PM and OVM This instruction is not affected by SXM. Description The content of PREG, shifted as defined by the PM status bits, is subtracted from the content of the accumulator.
  • Page 314 Syntax SPH dma SPH ind [, AR n ] Operands dma: ind: Opcode SPH dma SPH ind [, AR n ] Note: Execution Increment PC, then ... 16 MSBs of shifted (PREG) Status Bits Affected by Description The 16 high-order bits of the PREG, shifted as specified by the PM bits, are stored in data memory.
  • Page 315 Store High PREG Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 7-162 Cycles for a Repeat (RPT) Execution of an SPH Instruction DARAM 2n+nd 2n+nd DAT3 ;(DP = 4: addresses 0200h–027Fh, ;PM = 0: no shift) Before Instruction PREG...
  • Page 316 Syntax SPL dma SPL ind [, AR n ] Operands dma: ind: Opcode SPL dma SPL ind [, AR n ] Note: Execution Increment PC, then ... 16 LSBs of shifted (PREG) Status Bits Affected by Description The 16 low-order bits of the PREG, shifted as specified by the PM bits, are stored in data memory.
  • Page 317 Store Low PREG Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 Example 2 7-164 Cycles for a Repeat (RPT) Execution of an SPL Instruction DARAM 2n+nd 2n+nd DAT5 ;(DP = 4: addresses 0200h–027Fh, ;PM = 2: left shift of four) Before Instruction PREG...
  • Page 318 Syntax SPLK # lk , dma SPLK # lk , ind [, AR n ] Operands dma: ind: SPLK #lk, dma Opcode SPLK #lk, ind [ , AR n ] Note: Execution Increment PC, then ... data-memory address Status Bits None Description The SPLK instruction allows a full 16-bit pattern to be written into any data...
  • Page 319 SPLK Store Long-Immediate Value to Data Memory Example 2 SPLK #1111h,*+,AR4 Before Instruction After Instruction 300h 301h Data Memory Data Memory 300h 300h 1111h 7-166...
  • Page 320: Product Shift Modes

    Syntax SPM constant Operands constant: Opcode Execution Increment PC, then ... constant Status Bits Affects This instruction is not affected by SXM. Description The two LSBs of the instruction word are copied into the product shift mode (PM) bits of status register ST1 (bits 1 and 0 of ST1). The PM bits control the mode of the shifter at the output of the PREG.
  • Page 321 SQRA Square Value and Accumulate Previous Product Syntax SQRA dma SQRA ind [, AR n ] Operands dma: ind: SQRA dma Opcode SQRA ind [, AR n ] Note: Execution Increment PC, then ... (ACC) + shifted (PREG) (data-memory address) (TREG) Affected by Status Bits...
  • Page 322 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 SQRA Example 2 SQRA Square Value and Accumulate Previous Product Cycles for a Repeat (RPT) Execution of an SQRA Instruction DARAM n+nd n+nd DAT30...
  • Page 323 SQRS Square Value and Subtract Previous Product Syntax SQRS dma SQRS ind [, AR n ] Operands dma: ind: Opcode SQRS dma SQRS ind [, AR n ] Note: Execution Increment PC, then ... (ACC) – shifted (PREG) (data-memory address) (TREG) Status Bits Affected by...
  • Page 324 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 SQRS Example 2 SQRS Square Value and Subtract Previous Product Cycles for a Repeat (RPT) Execution of an SQRS Instruction DARAM n+nd n+nd DAT9...
  • Page 325 Store Status Register Syntax SST # m , dma SST # m , ind [, AR n ] Operands dma: ind: SST #0, dma Opcode SST #0 , ind [, AR n ] Note: SST #1, dma SST #1 , ind [, AR n ] Note: Execution Increment PC, then ...
  • Page 326 Status registers ST0 and ST1 are defined in Section 3.5, Status Registers ST0 and ST1 , on page 3-15. Words Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Operand DARAM SARAM External †...
  • Page 327 Subtract From Accumulator Syntax SUB dma [, shift ] SUB dma ,16 SUB ind [, shift [, AR n ] ] SUB ind ,16[ , AR n ] SUB # k SUB # lk [, shift ] Operands dma: shift: ind: SUB dma [ , shift ] Opcode...
  • Page 328 Execution Increment PC, then ... Event (ACC) – ((data-memory address) (ACC) – ( (data-memory address) (ACC) – k (ACC) – lk Status Bits Affected by OVM and SXM OVM and SXM Description In direct, indirect, and long immediate addressing, the content of the ad- dressed data-memory location or a 16-bit constant are left shifted and sub- tracted from the accumulator.
  • Page 329 Subtract From Accumulator Cycles Cycles for a Single SUB Instruction (Using Direct and Indirect Addressing) Operand DARAM SARAM External † If the operand and the code are in the same SARAM block. Cycles for a Repeat (RPT) Execution of an SUB Instruction (Using Direct Operand DARAM SARAM...
  • Page 330 Example 3 Example 4 Before Instruction 301h Data Memory 301h ;(SXM = 1: sign-extension mode) Before Instruction #0FFFh,4 ;(Left shift by four, SXM = 0) Before Instruction 0FFFFh Assembly Language Instructions Subtract From Accumulator After Instruction Data Memory 301h After Instruction FFFFFFFFh After Instruction 300h...
  • Page 331 SUBB Subtract From Accumulator With Borrow Syntax SUBB dma SUBB ind [, AR n ] Operands dma: ind: Opcode SUBB dma SUBB ind [, AR n ] Note: Execution Increment PC, then ... (ACC) – (data-memory address) – (logical inversion of C ) Affected by Status Bits This instruction is not affected by SXM.
  • Page 332 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 SUBB Example 2 SUBB In the first example, C is originally zeroed, presumably from the result of a pre- vious subtract instruction that performed a borrow. The effective operation per- formed was 6 –...
  • Page 333 SUBC Conditional Subtract Syntax SUBC dma SUBC ind [, AR n ] Operands dma: ind: SUBC dma Opcode SUBC ind [, AR n ] Note: Execution For (ACC) Increment PC, then ... (ACC) – [(data-memory address) If ALU output Then (ALU output) Else (ACC) Status Bits Affects...
  • Page 334 SUBC affects OV but is not affected by OVM; therefore, the accumulator does not saturate upon positive or negative overflows when executing this instruc- tion. The carry bit is affected in the normal manner during this instruction: the carry bit is cleared (C = 0) if the result of the subtraction generates a borrow and is set (C = 1) if it does not generate a borrow.
  • Page 335 SUBS Subtract From Accumulator With Sign Extension Suppressed Syntax SUBS dma SUBS ind [, AR n ] Operands dma: ind: SUBS dma Opcode SUBS ind [, AR n ] Note: Execution Increment PC, then ... (ACC) – (data-memory address) Status Bits Affected by This instruction is not affected by SXM.
  • Page 336 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 SUBS Example 2 SUBS Subtract From Accumulator With Sign Extension Suppressed Cycles for a Repeat (RPT) Execution of an SUBS Instruction DARAM n+nd n+nd...
  • Page 337 SUBT Subtract From Accumulator With Shift Specified by TREG Syntax SUBT dma SUBT ind [, AR n ] Operands dma: ind: SUBT dma Opcode SUBT ind [, AR n ] Note: Execution Increment PC, then ... (ACC) – [(data-memory address) If SXM = 1 Then (data-memory address) is sign-extended.
  • Page 338 Cycles Operand DARAM SARAM External † If the operand and the code are in the same SARAM block. Operand DARAM SARAM External † If the operand and the code are in the same SARAM block. Example 1 SUBT Example 2 SUBT Subtract From Accumulator With Shift Specified by TREG Cycles for a Single SUBT Instruction...
  • Page 339 TBLR Table Read Syntax TBLR dma TBLR ind [, AR n ] Operands dma: ind: Opcode TBLR dma TBLR ind [, AR n ] Note: Execution Increment PC, then ... (PC) (ACC(15:0)) (pma) For indirect, modify (current AR) and (ARP) as specified, (PC) + 1 While (repeat counter) (pma)
  • Page 340 Cycles Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External † If the destination operand and the code are in the same SARAM block Cycles for a Repeat (RPT) Execution of a TBLR Instruction Operand Source: DARAM/ROM...
  • Page 341 TBLR Table Read Cycles for a Repeat (RPT) Execution of a TBLR Instruction (Continued) Operand Source: DARAM/ROM Destination: SARAM Source: SARAM ‡ Destination: SARAM Source: External n+2+np Destination: SARAM Source: DARAM/ROM 2n+2+nd Destination: External Source: SARAM 2n+2+nd Destination: External Source: External 4n+np Destination: External †...
  • Page 342 Syntax TBLW dma TBLW ind [, AR n ] Operands dma: ind: Opcode TBLW dma TBLW ind [, AR n ] Note: Execution Increment PC, then ... (PC+1) (ACC(15:0)) (data-memory address) For indirect, modify (current AR) and (ARP) as specified (PC) + 1 While (repeat counter) (data-memory address)
  • Page 343 TBLW Table Write Cycles Operand Source: DARAM/ROM Destination: DARAM Source: SARAM Destination: DARAM Source: External Destination: DARAM Source: DARAM/ROM Destination: SARAM Source: SARAM Destination: SARAM Source: External Destination: SARAM Source: DARAM/ROM Destination: External Source: SARAM Destination: External Source: External Destination: External †...
  • Page 344 Cycles for a Repeat (RPT) Execution of a TBLW Instruction (Continued) Operand Source: DARAM/ROM Destination: SARAM Source: SARAM ‡ Destination: SARAM Source: External n+2+nd Destination: SARAM Source: DARAM/ROM 2n+2+np Destination: External Source: SARAM 2n+2+np Destination: External Source: External 4n+nd Destination: External †...
  • Page 345 TRAP Software Interrupt Syntax TRAP Operands None Opcode Execution (PC) + 1 Status Bits Not affected by INTM; does not affect INTM. Description The TRAP instruction is a software interrupt that transfers program control to program-memory location 22h and pushes the program counter (PC) plus 1 onto the hardware stack.
  • Page 346 Syntax XOR dma XOR ind [, AR n ] XOR # lk , [, shift ] XOR # lk, 16 Operands dma: shift: ind: XOR dma Opcode XOR ind [, AR n ] Note: XOR # lk [, shift ] XOR # lk, 16 Execution Increment PC, then ...
  • Page 347 Exclusive OR With Accumulator Status Bits None Description With direct or indirect addressing, the low half of the accumulator value is exclusive ORed with the content of the addressed data memory location, and the result replaces the low half of the accumulator value; the upper half of the accumulator value is unaffected.
  • Page 348 Example 1 Example 2 Example 3 DAT127 ;(DP = 511: addresses FF80h–FFFFh) Before Instruction Data Memory 0FFFFh 0F0F0h 12345678h *+,AR0 Before Instruction 300h Data Memory 300h 0FFFFh 1234F0F0h #0F0F0h,4 ;(First shift data value left by ;four) Before Instruction 11111010h Assembly Language Instructions Exclusive OR With Accumulator After Instruction Data Memory...
  • Page 349 ZALR Zero Low Accumulator and Load High Accumulator With Rounding Syntax ZALR dma ZALR ind [, AR n ] Operands dma: ind: Opcode ZALR dma ZALR ind [, AR n ] Note: Execution Increment PC, then ... (data-memory address) 8000h Status Bits None Description...
  • Page 350 Operand DARAM SARAM External † If the operand and the code are in the same SARAM block Example 1 ZALR Example 2 ZALR Zero Low Accumulator and Load High Accumulator With Rounding Cycles for a Repeat (RPT) Execution of a ZALR Instruction DARAM n+nd n+nd...
  • Page 351 This chapter discusses on-chip peripherals connected to the ’C2xx CPU and their control registers. The on-chip peripherals are controlled through memory-mapped registers. The operations of the timer and the serial ports are synchronized to the processor through interrupts and interrupt polling. The ’C2xx on-chip peripherals are: Clock generator Timer...
  • Page 352: Peripheral Register Locations And Reset Conditions

    Control of On-Chip Peripherals 8.1 Control of On-Chip Peripherals The on-chip peripherals are controlled by accessing control registers that are mapped to on-chip I/O space. Data is also transferred to and from the peripher- als through these registers. Setting and clearing bits in these registers can en- able, disable, initialize, and dynamically reconfigure the on-chip peripherals.
  • Page 353 Table 8–1. Peripheral Register Locations and Reset Conditions (Continued) I/O Address Register Register Name Name ’C209 IOSR – – FFFCh FFFDh FFFEh WSGR FFFFh Other ’C2xx Reset Value Effects at Reset FFF6h 18xxh I/O status register. Auto-baud alignment is disabled. Error and status flags are reset. The lower eight bits are dependent on the values on pins IO0, IO1, IO2, and IO3 at reset.
  • Page 354: Using The Internal Oscillator

    Clock Generator 8.2 Clock Generator The high pulse of the master clock output signal (CLKOUT1) signifies the logic phase of the device (the phase when values are changed), while the low pulse signifies the latch phase (the phase when values are latched). CLKOUT1 de- termines much of the device’s operational speed.
  • Page 355: Clock Generator Options

    External Oscillator. CLKIN is the output of an external oscillator, which is connected to the CLKIN/X2 pin. The X1 pin must be left unconnected. See Figure 8–2. Figure 8–2. Using an External Oscillator Regardless of the method used to generate CLKOUT1, CLKOUT1 is also available at the CLKOUT1 pin, unless the pin is turned off by the CLK register (see Section 8.3).
  • Page 356: C2Xx Input Clock Modes

    Clock Generator Table 8–2. ’C2xx Input Clock Modes Clock CLKOUT1 Rate Mode CLKOUT1 = CLKIN CLKOUT1 = CLKIN CLKOUT1 = CLKIN CLKOUT1 = CLKIN Remember the following when configuring the clock mode: The clock mode configuration cannot be dynamically changed. After you change the levels on DIV1 and DIV2, the mode is not changed until a hard- ware reset is executed (RS low).
  • Page 357: C2Xx Clk Register - I/O-Space Address Ffe8H

    8.3 CLKOUT1-Pin Control (CLK) Register You can use bit 0 of the CLK register to turn off the pin for the master clock out- put signal (CLKOUT1). The CLK register is located at address FFE8h in I/O space and has the organization shown in Figure 8–3. Figure 8–3.
  • Page 358: Timer Functional Block Diagram

    Timer 8.4 Timer The ’C2xx features an on-chip timer with a 4-bit prescaler. This timer is a down counter that can be stopped, restarted, reset, or disabled by specific status bits. You can use the timer to generate periodic CPU interrupts. Figure 8–4 shows a functional block diagram of the timer.
  • Page 359: Timer Operation

    The TINT request automatically sets the TINT flag bit in the interrupt flag regis- ter (IFR). You can mask or unmask the request with the interrupt mask register (IMR). If you are not using the timer, mask TINT so that it does not cause an unexpected interrupt.
  • Page 360: Timer Control Register (Tcr)

    Timer sor v are the TIM and PRD, respectively. Both are16-bit registers mapped to I/O space. The 4-bit TDDR (timer divide-down register) and the 4-bit PSC (prescaler counter) are contained in the timer control register (TCR) described in subsec- tion 8.4.2. The TIM (timer counter register) and the PRD (timer period register) are 16-bit registers described in subsection 8.4.3.
  • Page 361: C2Xx Timer Control Register (Tcr) - I/O-Space Address Fff8H

    Figure 8–5. ’C2xx Timer Control Register (TCR) — I/O-Space Address FFF8h É É É É É É É É Reserved É É É É É É É É Note: 0 = Always read as zeros; R = Read access; W = Write access; value following dash (–) is value after reset. Bits 15–12 Reserved.
  • Page 362: Timer Counter Register (Tim) And Timer Period Register (Prd)

    Timer Bit 4 TSS — Timer stop status bit. TSS stops or starts the timer. At reset, TSS is cleared to 0 and the timer immediately starts. TSS = 0 TSS = 1 Bits 3–0 TDDR — Timer divide-down register. Every (TDDR + 1) CLKOUT1 cycles, the timer counter register (TIM) decrements by one.
  • Page 363: Setting The Timer Interrupt Rate

    8.4.4 Setting the Timer Interrupt Rate When the divide-down value (TDDR) is 0, you can program the timer to gener- ate an interrupt (TINT) every 2 to 65 536 cycles by programming the period register (PRD) from 0 to 65 535 (FFFFh). When TDDR is nonzero (1 to 15), the timer interrupt rate decreases.
  • Page 364: Wait-State Generator

    Wait-State Generator 8.5 Wait-State Generator Wait states are necessary when you want to interface the ’C2xx with slower external logic and memory. By adding wait states, you lengthen the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that memory or port.
  • Page 365: C2Xx Wait-State Generator Control Register (Wsgr)

    state generator, see subsection 11.4.3 on page 11-16. To avoid bus conflicts, all writes to external addresses take at least two cycles. Figure 8–6. ’C2xx Wait-State Generator Control Register (WSGR) — I/O-Space Address FFFCh É É É É É É É É Reserved É...
  • Page 366: Setting The Number Of Wait States With The 'C2Xx Wsgr Bits

    Wait-State Generator Table 8–4 shows how to set the number of wait states you want for each type of off-chip memory. For example, if you write 1s to bits 0 through 5, the device will generate seven wait states for off-chip lower program memory and seven wait states for off-chip upper program memory.
  • Page 367: General-Purpose I/O Pins

    8.6 General-Purpose I/O Pins The ’C2xx provides pins that can be used to supply input signals from an exter- nal device or output signals to an external device. These pins are not bound to specific uses; rather, they can provide input or output signals for a great vari- ety purposes.
  • Page 368: Output Pin Xf

    General-Purpose I/O Pins Figure 8–7. BIO Timing Diagram Example CLKOUT1 8.6.2 Output Pin XF The XF pin is the external flag output pin. If you connect XF to an input pin of another processor, you can use XF as a signal to other processor. The most recent XF value is latched in the ’C2xx, and that value is indicated by the XF status bit of status register ST1.
  • Page 369 Synchronous Serial Port The ’C2xx devices have a synchronous serial port that provides direct communication with serial devices such as codecs (coder/decoders) and serial A/D converters. The serial port may also be used for intercommunication between processors in multiprocessing applications. The synchronous serial port offers these features: Two four-word-deep FIFO buffers Interrupts generated by the FIFO buffers...
  • Page 370: Overview Of The Synchronous Serial Port

    Overview of the Synchronous Serial Port 9.1 Overview of the Synchronous Serial Port Both receive and transmit operations of the synchronous serial port have a four-word-deep first-in, first-out (FIFO) buffer. The FIFO buffers reduce the amount of CPU overhead inherent in servicing transmit or receive data by re- ducing the number of transmit or receive interrupts that occur during a transfer.
  • Page 371: Components And Basic Operation

    9.2 Components and Basic Operation The synchronous serial port has several hard-wired parts, including two FIFO buffers and six signal pins. Figure 9–1 shows how the components of the syn- chronous serial port are interconnected. Figure 9–1. Synchronous Serial Port Block Diagram SDTR receive (-3) Control logic...
  • Page 372: Ssp Interface Pins

    Components and Basic Operation Data signal. The data signal carries the actual data that is transferred in the transmit/receive operation. The data signal transmit pin (DX) of one device should be connected to the data signal receive (DR) pin on another device.
  • Page 373: Way Serial Port Transfer With External Frame Sync And External Clock

    Figure 9–2. 2-Way Serial Port Transfer With External Frame Sync and External Clock TLC320AD55C Analog signal Analog signal Legend: D OUT Transmit data 9.2.2 FIFO Buffers and Registers The synchronous serial port (SSP) has two four-level transmit and receive FIFO buffers (shown at the center of Figure 9–1 on page 9-3). Two on-chip registers allow you to access the FIFO buffers and control the op- eration of the port: Synchronous data transmit and receive register (SDTR).
  • Page 374: Basic Operation

    Components and Basic Operation 9.2.3 Interrupts The synchronous serial port (SSP) has two hardware interrupts that let the pro- cessor know when the FIFO buffers need to be serviced: Transmit interrupts (XINTs) cause a branch to address 000Ah in program space whenever the transmit-interrupt trigger condition is met.
  • Page 375 Receiving a word through the serial port typically is done as follows: 1) Data from the DR pin is shifted, bit-by-bit (MSB first), into the receive shift register (RSR). 2) When the RSR is full, the RSR copies the data to the receive FIFO buffer. 3) The process then does one of two things, depending upon the state of the receive FIFO buffer: If the receive FIFO buffer is not full, the process repeats from step 1.
  • Page 376: Controlling And Resetting The Port

    Controlling and Resetting the Port 9.3 Controlling and Resetting the Port The synchronous serial port control register (SSPCR) controls the operation of the synchronous serial port. To configure the serial port, a total of two writes to the SSPCR are necessary: 1) Write your choices to the configuration bits and place the port in reset by writing zeros to SSPCR bits XRST and RRST.
  • Page 377: Run And Emulation Modes

    Table 9–2. Run and Emulation Modes Note: If an option besides immediate stop is chosen for the receiver, an overflow error is possible. The default mode (selected at reset) is immediate stop. Bit 13 TCOMP — Transmission complete. This bit is cleared to 0 when all data in the transmit FIFO buffer has been transmitted (the buffer is empty) and is set to 1 when new data is written to the transmit FIFO buffer (the buffer is not empty).
  • Page 378: Controlling Receive Interrupt Generation By Writing To Bits Fr1 And Fr0

    Controlling and Resetting the Port Bits 9–8 FR1, FR0 — FIFO receive-interrupt bits. The values you write to FR0 and FR1 set an interrupt trigger condition based on the contents of the receive FIFO buffer. When this condition is met, a receive interrupt (RINT) is gener- ated and the data can be transferred in from the FIFO buffer using the IN instruction.
  • Page 379 Bit 3 TXM — Transmit mode. This bit determines the source device for the frame synchronization (frame sync) pulse for transmissions. It configures the transmit frame sync pin (FSX) as an output or as in input. Note that the receive frame sync pin (FSR) is always configured as an input. TXM = 0 TXM = 1 Bit 2...
  • Page 380: Selecting A Mode Of Operation (Bit 1 Of The Sspcr)

    Controlling and Resetting the Port Bit 0 DLB — Digital loopback mode. The DLB bit can be used to put the serial port in digital loopback mode. DLB = 0 DLB = 1 9.3.1 Selecting a Mode of Operation (Bit 1 of the SSPCR) Different applications require different modes of operation for the serial port.
  • Page 381: Resetting The Synchronous Serial Port (Bits 4 And 5 Of The Sspcr)

    A transmit frame sync pulse marks the start of a data transmission. The syn- chronous serial port can transmit using the internal frame sync source or using an external source: To use internal frame sync pulses, set the TXM bit in the SSPCR to 1. To use external frame sync pulses: 1) Connect the frame sync source to the FSX pin of the transmitter and to 2) Set the TXM bit in the SSPCR to 0 to enable external frame syncs.
  • Page 382 Controlling and Resetting the Port 1) Create interrupt service routines for XINTs and RINTs and include a branch to each service routine at the appropriate interrupt vector address: 2) Select when you want interrupts to occur and set the FR0, FR1, FT0, and FT1 bits accordingly.
  • Page 383: Managing The Contents Of The Fifo Buffers

    Managing the Contents of the FIFO Buffers 9.4 Managing the Contents of the FIFO Buffers The SDTR is a read/write register (at I/O address FFF0h) that is used to send data to the transmit FIFO buffer and to extract data from the receive FIFO buffer.
  • Page 384: Transmitter Operation

    Transmitter Operation 9.5 Transmitter Operation Transmitter operation is different in continuous and burst modes. Other differ- ences also depend on whether an internal or an external frame sync is used. 9.5.1 Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1) Use burst mode transmission with internal frame sync to transfer short packets at rates lower than maximum packet frequency while using an internal frame sync generator.
  • Page 385: Burst Mode Transmission With Internal Frame Sync And

    If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. The burst mode can be discontinued (changed to continuous mode) only by a serial-port or device reset.
  • Page 386: Burst Mode Transmission With External Frame Sync (Fsm = 1, Txm = 0)

    Transmitter Operation 9.5.2 Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0) Use burst mode transmission with external frame sync to transfer short pack- ets at rates lower than maximum packet frequency while using an external frame sync generator.
  • Page 387: Burst Mode Transmission With External Frame Sync

    Transmitter Operation Figure 9–5. Burst Mode Transmission With External Frame Sync CLKX XINT XSR loaded XSR loaded from buffer from buffer Synchronous Serial Port 9-19...
  • Page 388: Continuous Mode Transmission With Internal Frame Sync (Fsm = 0, Txm = 1)

    Transmitter Operation 9.5.3 Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1) Use continuous mode transmission with internal frame sync to transfer long packets at maximum packet frequency while using an internal frame sync gen- erator. Place the transmitter in continuous mode with internal frame sync by setting the FSM bit to 0 and the TXM bit to 1.
  • Page 389: Continuous Mode Transmission With Internal Frame Sync

    Transmitter Operation If the SDTR is loaded with a new word while the transmit FIFO buffer is full, the new word will be lost; the FIFO buffer will not accept any more than four words. Continuous mode can be discontinued (changed to burst mode) only by a seri- al-port or device reset.
  • Page 390 Transmitter Operation 9.5.4 Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0) Use continuous mode transmission with external frame sync to transfer long packets at maximum packet frequency while using an external frame sync generator. Place the transmitter in continuous mode with external frame sync by setting the FSM bit to 0 and the TXM bit to 0.
  • Page 391: Continuous Mode Transmission With External Frame Sync

    Transmitter Operation The continuous mode can be discontinued (changed to burst mode) only by a serial-port or device reset. Changing the FSM bit during transmit or halt will not necessarily cause a switch to burst mode. Figure 9–7. Continuous Mode Transmission With External Frame Sync CLKX XINT XSR loaded...
  • Page 392: Receiver Operation

    Receiver Operation 9.6 Receiver Operation Receiver operation is different in continuous and burst modes. The receiver does not generate frame sync pulses; it always takes the frame sync pulse as an input. In selecting the proper receive mode, note that the mode for the receiver must match the mode for the transmitter.
  • Page 393: Continuous Mode Reception

    If a frame sync pulse occurs during reception, reception is restarted, and the bits that were shifted into the RSR before the pulse are lost. Figure 9–8. Burst Mode Reception CLKR RINT 9.6.2 Continuous Mode Reception Use continuous mode receive to transfer long packets at maximum packet fre- quency.
  • Page 394: Continuous Mode Reception

    Receiver Operation 3) The remaining bits in the word are then shifted into the RSR, one by one at the falling edge of each consecutive clock cycle. 4) After all bits have been received, if the FIFO buffer is not full, the contents of the RSR are copied to the receive FIFO buffer.
  • Page 395: Troubleshooting

    9.7 Troubleshooting The synchronous serial port uses three bits for troubleshooting and testing. In addition to using these three bits, you must be able to identify special error conditions that may occur in actual transfers. Error conditions result from an unprogrammed event occurring to the serial port.
  • Page 396: Run And Emulation Modes

    Troubleshooting Table 9–6. Run and Emulation Modes Note: If an option besides immediate stop is chosen for the receiver, an overflow error is possible. The default mode (selected at reset) is immediate stop. DLB enables or disables digital loopback mode: When you enable digital loopback mode, the transmit data (DX) and frame sync (FSX) signals become internally connected to the receive data (DR) and frame sync (FSR) signals.
  • Page 397: Burst Mode Error Conditions

    9.7.2 Burst Mode Error Conditions The following are descriptions of errors that can occur in burst mode: Underflow. Underflow is caused if an external FSX occurs, and there are no new words in the transmit FIFO buffer. Upon receiving the FSX (gener- ally, from an external clock source), transmitter resends the previous word;...
  • Page 398 Troubleshooting Overflow. Overflow occurs when the RSR has new data to pass to the receive FIFO buffer but the FIFO buffer is full. Overflow errors are fatal to a reception. For as long as the FIFO buffer is full, any incoming words will be lost.
  • Page 399: Asynchronous Serial Port

    Asynchronous Serial Port The ’C2xx has an asynchronous serial port that can be used to transfer data to and from other devices. The port has several important features: Full-duplex transmit and receive operations at the maximum transfer rate Data-word length of eight bits for both transmit and receive Capability for using one or two stop bits Double buffering in all modes to transmit and receive data Adjustable baud rate of up to 250,000 10-bit characters per second...
  • Page 400: Overview Of The Asynchronous Serial Port

    Overview of the Asynchronous Serial Port 10.1 Overview of the Asynchronous Serial Port The on-chip asynchronous serial port (ASP) provides easy serial data commu- nication between host CPUs and the ’C2xx or between two ’C2xx devices. The asynchronous mode of data communication is often referred to as UART (uni- versal asynchronous receive and transmit).
  • Page 401: Components And Basic Operation

    10.2 Components and Basic Operation Figure 10–1 shows the main components of the asynchronous serial port. Figure 10–1. Asynchronous Serial Port Block Diagram Control logic (receive) TXRXINT Sequence control CLKOUT1 10.2.1 Signals Two types of signals are used in asynchronous serial port (ASP) operations: Data signal.
  • Page 402: Baud-Rate Generator

    Components and Basic Operation Table 10–1. Asynchronous Serial Port Interface Pins Pin Name 10.2.2 Baud-Rate Generator The baud-rate generator is a clock generator for the asynchronous serial port. The output rate of the generator is a fraction of the CLKOUT1 rate and is con- trolled by a 16-bit register, BRD, that you can read from and write to at I/O ad- dress FFF7h.
  • Page 403: Interrupts

    I/O status register (IOSR). Bits in the IOSR indicate detection of the in- coming baud rate, various error conditions, the status of data transfers, detection of a break on the RX pin, the status of pins IO3–IO0, and detec- tion of changes on pins IO3–IO0. The IOSR is at address FFF6h in I/O space.
  • Page 404: Basic Operation

    Components and Basic Operation 10.2.5 Basic Operation Figure 10–2 shows a typical serial link between a ’C2xx device and any host CPU. In this mode of communication, any 8-bit character can be transmitted or received serially by way of the transmit data pin (TX) or the receive data pin (RX), respectively.
  • Page 405: Asynchronous Serial Port Control Register (Aspcr)

    10.3 Controlling and Resetting the Port The asynchronous serial port is programmed through three on-chip registers mapped to I/O space: the asynchronous serial port control register (ASPCR), the I/O status register (IOSR), and the baud-rate divisor register (BRD). This section describes the contents of each of these registers and also explains the use of associated control features.
  • Page 406 Controlling and Resetting the Port Bits 12–10 Reserved. Always read as 0s. Bit 9 DIM — Delta interrupt mask. DIM selects whether or not delta interrupts are asserted on the TXRXINT interrupt line. A delta interrupt is generated by a change on one of the general-purpose I/O pins (IO3, IO2, IO1, or IO0). DIM = 0 DIM = 1 Bit 8...
  • Page 407: Controlling And Resetting The Port

    Bit 3 CIO3 — Configuration bit for IO3. CIO3 configures I/O pin 3 (IO3) as an input or as an output. CIO3 = 0 CIO3 = 1 Bit 2 CIO2 — Configuration bit for IO2. CIO2 configures I/O pin 2 (IO2) as an input or as an output.
  • Page 408: I/O Status Register (Iosr) - I/O-Space Address Fff6H

    Controlling and Resetting the Port 10.3.2 I/O Status Register (IOSR) The IOSR returns the status of the asynchronous serial port and of I/O pins IO0–IO3. The IOSR is a 16-bit, on-chip register mapped to address FFF6h in I/O space. Figure 10–4 shows the fields in the IOSR, and bit descriptions fol- low the figure.
  • Page 409 Bit 11 THRE — Transmit register (ADTR) empty indicator. THRE is set to 1 when the contents of the transmit register (ADTR) are transferred to the transmit shift register (AXSR). THRE is reset to 0 by the loading of the trans- mit register with a new character.
  • Page 410 Controlling and Resetting the Port Bit 7 DIO3 — Change detect bit for IO3. DIO3 indicates whether a change has occurred on the IO3 pin. A change can be detected only when IO3 is config- ured as an input by the CIO3 bit of the ASPCR (CIO3 = 0) and the serial port is enabled by the URST bit of the ASPCR (URST = 1).
  • Page 411: Baud-Rate Divisor Register (Brd)

    Bit 3 IO3 — Status bit for IO3. When the IO3 pin is configured as an input (by the CIO3 bit of the ASPCR), this bit reflects the current level on the IO3 pin. IO3 = 0 IO3 = 1 Bit 2 IO2 —...
  • Page 412: Using Automatic Baud-Rate Detection

    Controlling and Resetting the Port Table 10–2. Common Baud Rates and the Corresponding BRD Values Baud CLKOUT1 = 20 MHz Rate (50 ns) 1200 0411 2400 0208 4800 0104 9600 0082 19200 0041 10.3.4 Using Automatic Baud-Rate Detection The ASP contains auto-baud detection logic, which allows the ASP to lock to the incoming data rate.
  • Page 413: Using I/O Pins Io3, Io2, Io1, And Io0

    10.3.5 Using I/O Pins IO3, IO2, IO1, and IO0 Pins IO3, IO2, IO1, and IO0 can be individually configured as inputs or outputs and can be used as handshake control for the asynchronous serial port or as general-purpose I/O pins. They are software-controlled through the asynchro- nous serial port control register (ASPCR) and the I/O status register (IOSR), as shown in Figure 10–5.
  • Page 414: Viewing The Status Of Pins Io0-Io3 With Iosr Bits Io0-Io3 And Dio0-Dio3

    Controlling and Resetting the Port When pins IO0–IO3 are configured as inputs When pins IO0–IO3 are configured as inputs, the eight LSBs of the IOSR allow you to monitor these four pins. Each of the IOSR bits 3–0, called IO3, IO2, IO1, and IO0, can be used to read the current logic level (high or low) of the signal at the corresponding pin.
  • Page 415: Using Interrupts

    10.3.6 Using Interrupts The asynchronous serial port interrupt (TXRXINT) can be generated by three types of interrupts: Transmit interrupts. A transmit interrupt is generated when the ADTR empties during transmission. This indicates that the port is ready to accept a new transmit character. In addition to generating the interrupt, the port sets the THRE bit of the IOSR to 1.
  • Page 416 Controlling and Resetting the Port TXRXINT leads the CPU to interrupt vector location 000Ch in program memory. The branch at that location should lead to an interrupt service routine that identifies the cause of the interrupt and then acts accordingly. TXRXINT has a priority level of 9 (1 being highest).
  • Page 417: Data Transmit

    10.4 Transmitter Operation The transmitter consists of an 8-bit transmit register (ADTR) and an 8-bit trans- mit shift register (AXSR). Data to be transmitted is written to the ADTR, and then the port transfers the data to the AXSR. Data written to the transmit regis- ter should be written in right-justified form, with the LSB as the rightmost bit.
  • Page 418: Data Receive

    Receiver Operation 10.5 Receiver Operation The receiver includes two internal 8-bit registers: the receive register (ADTR) and receive shift register (ARSR). The data received at the RX pin should have the serial form shown in Figure 10–7 (the number of stop bits required de- pends on the value of the STB bit in the ASPCR).
  • Page 419 All ’C2xx devices use the same central processing unit (CPU), bus structure, and instruction set, but the ’C209 has some notable differences. This chapter compares features on the ’C209 with those on other ’C2xx devices and then provides information specific to the ’C209 in the areas of memory and I/O spaces, interrupts, and on-chip peripherals.
  • Page 420: C209 Versus Other 'C2Xx Devices

    ’C209 Versus Other ’C2xx Devices 11.1 ’C209 Versus Other ’C2xx Devices This section explains the differences between the ’C209 and other ’C2xx de- vices and concludes with a table to help you find the other information in this manual that applies to the ’C209. 11.1.1 What Is the Same The following components and features are identical on all ’C2xx devices, in- cluding the ’C209:...
  • Page 421 Memory and I/O Spaces: Interrupts: 11.1.3 Where to Find the Information You Need About the TMS320C209 For information about: Assembly language instructions Clock generator Data-address generation I/O Space The I/O addresses of the peripheral registers are different on the ’C209. The ’C209 does not support the ’C2xx HOLD operation.
  • Page 422 ’C209 Versus Other ’C2xx Devices For information about: Interrupts Memory Pipeline Power-down mode Program-address generation Program control Stack Status registers Timer Wait-state generator 11-4 Main description Vector locations Flag and mask registers Interrupt acknowledge pin Main description Address maps Configuration Main description Configuration Main description...
  • Page 423: C209 Memory And I/O Spaces

    11.2 ’C209 Memory and I/O Spaces The ’C209 does not have an on-chip boot loader and does not support the ’C2xx HOLD operation. Figure 11–1 shows the ’C209 address map. The on- chip program and data memory available on the ’C209 consists of: ROM (4K words, for program memory) SARAM (4K words, for program and/or data memory) DARAM B0 (256 words, for program or data memory)
  • Page 424: C209 Address Maps

    ’C209 Memory and I/O Spaces Figure 11–1.’C209 Address Maps ’C209 Program 0000h Interrupts (on-chip) (MP/MC = 0) Interrupts (external) (MP/MC = 1) 003Fh On-chip ROM (MP/MC = 0) External (MP/MC = 1) 0FFFh 1000h On-chip SARAM (RAMEN = 1); External (RAMEN = 0) 1FFFh 2000h...
  • Page 425: Do Not Write To Reserved Addresses

    Do Not Write to Reserved Addresses To avoid unpredictable operation of the processor, do not write to any addresses labeled Reserved. This includes any data-memory address in the range 0000h–005Fh that is not designated for an on-chip register and any I/O address in the range FF00h–FFFFh that is not designated for an on-chip register.
  • Page 426: C209 Program-Memory Configuration Options

    ’C209 Memory and I/O Spaces (4K) are mapped to external data memory. Thus, a total of 8K additional addresses (4K program and 4K data) are available for external memory. DARAM blocks B1 and B2 are fixed, but DARAM block B0 may be mapped to program space or data space, depending on the value of the CNF bit (bit 12 of status register ST1): When CNF = 0, B0 is mapped to data space and is accessible at data ad-...
  • Page 427: C209 Data-Memory Configuration Options

    Table 11–2. ’C209 Data-Memory Configuration Options DARAM B0 RAMEN (hex) 0200–02FF – 0200–02FF – A portion of the on-chip I/O space contains the control registers listed in Table 11–3.The corresponding registers on other ’C2xx devices are not at the addresses shown in this table. When accessing the I/O-mapped registers on the ’C209, also keep in mind the following: The READY pin must be pulled high to permit reads from or writes to regis- ters mapped to internal I/O space.
  • Page 428: C209 Interrupts

    ’C209 Interrupts 11.3 ’C209 Interrupts Table 11–4 lists the interrupts available on the ’C209 and shows their vector locations. In addition, it shows the priority of each of the hardware interrupts. Note that a device reset can be initiated in either of two ways: by driving the RS pin low or by driving the RS pin high.
  • Page 429: C209 Interrupt Registers

    Table 11–4. ’C209 Interrupt Locations and Priorities (Continued) † † The K value is the operand used in an INTR instruction that branches to the corresponding interrupt vector location. ‡ The ’C209 has two pins for triggering a hardware reset: RS and RS. If either RS is driven low or RS is driven high, the device will be reset.
  • Page 430: C209 Interrupt Flag Register (Ifr) - Data-Memory Address 0006H

    ’C209 Interrupts Figure 11–2.’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h É É É É É É É É É É É É É É É É É Reserved É É É É É É É É É É É É É É É É É Note: 0 = Always read as zeros;...
  • Page 431: Iack Pin

    Figure 11–3.’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h É É É É É É É É É É É É É É É É É É Reserved É É É É É É É É É É É É É É É É É É Note: Note: 0 = Always read as zeros;...
  • Page 432: C209 On-Chip Peripherals

    ’C209 On-Chip Peripherals 11.4 ’C209 On-Chip Peripherals The ’C209 has these on-chip peripherals: Clock generator. The clock generator is fundamentally the same on all ’C2xx devices, including the ’C209. However, the ’C209 is limited to the two clock modes described in subsection 11.4.1. Timer.
  • Page 433: C209 Timer Control Register (Tcr) - I/O Address Fffch

    Table 11–5. ’C209 Input Clock Modes Clock Mode CLKOUT1 Rate Remember the following points when configuring the clock mode: The modes cannot be configured dynamically. After you change the level on CLKMOD, the mode is not changed until a hardware reset is executed (RS low or RS high).
  • Page 434: C209 Wait-State Generator

    ’C209 On-Chip Peripherals Bit 4 TSS — Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer immediately starts.
  • Page 435: C209 Wait-State Generator Control Register (Wsgr) - I/O Address Ffffh

    Figure 11–5.’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh É É É É É É É É É É É É É É É É É É Reserved É É É É É É É É É É É É É É É É É É Note: 0 = Always read as zeros;...
  • Page 436 For the status and control registers of the ’C2xx devices, this appendix summarizes: Their addresses Their reset values The functions of their bits Topic Addresses and Reset Values Register Descriptions ......... Appendix A Appendix A Register Summary...
  • Page 437: Reset Values Of The Status Registers

    Addresses and Reset Values A.1 Addresses and Reset Values The following tables list the ’C2xx registers, the addresses at which they can be accessed, and their reset values. Note that the registers mapped to internal I/O space on the ’C209 are at addresses different from those of other ’C2xx devices.
  • Page 438 Table A–3. Addresses and Reset Values of On-Chip Registers Mapped to I/O Space (Continued) I/O Address Name ’C209 Other ’C2xx IOSR – FFF6h – FFF7h FFFCh FFF8h FFFDh FFF9h FFFEh FFFAh WSGR FFFFh FFFCh Note: An x in an address represents four bits that are either not affected by reset or dependent on pin levels at reset. Reset Value Description 18xxh...
  • Page 439: A.2 Register Descriptions

    Register Descriptions A.2 Register Descriptions The following figures summarize the content of the ’C2xx status and control registers that are divided into fields. (The other registers contain no control bits; they simply hold a single 16-bit value.) Each figure in this section provides information in this way: The value shown in the register is the value after reset.
  • Page 440 Status Register ST0 Overflow mode Accumulator results overflow normally. Overflow mode selected Overflow flag Flag is reset Overflow detected in accumulator Auxiliary register pointer Selects the current auxiliary register (0, 1, 2, 3, 4, 5, 6, or 7) † This reserved bit is always read as 1. Writes have no effect. Status Register ST1 Sign-extension mode Sign extension suppressed...
  • Page 441 Register Descriptions ’C2xx Interrupt Flag Register (IFR) — Except ’C209 — Data-Memory Address 0006h É É É É É É É É É É É É É É É É É É † Reserved Receive interrupt flag Interrupt RINT not pending Interrupt RINT pending Transmit interrupt flag Interrupt XINT not pending...
  • Page 442 Interrupt Mask Register (IMR) — Except ’C209 — Data-Memory Address 0004h É É É É É É É É É É É É É É É É É É É É † Reserved Receive interrupt mask Interrupt RINT masked Interrupt RINT unmasked Transmit interrupt mask Interrupt XINT masked Interrupt XINT unmasked...
  • Page 443 Register Descriptions Interrupt Control Register (ICR) — I/O Address FFECh É É É É É É É É É É É É É É É É É É É É É É É É É É † Reserved INT2 flag INT3 flag INT3 not pending INT3 pending...
  • Page 444 Timer Control Register (TCR) — Except ’C209 — I/O Address FFF8h É É É É É É É É É É É É É É É É † Reserved Timer reload bit Write 1 to reload timer counters. Always read as 0 Timer prescaler counter Holds current prescale count for the timer Emulation/run mode...
  • Page 445 Register Descriptions Wait-State Generator Control Register (WSGR) — Except ’C209— I/O Address FFFCh É É É É É É É É É É É É É É É É † Reserved Data wait states I/O wait states 0 wait states 1 wait state 2 wait states 3 wait states...
  • Page 446 CLK Register — I/O Address FFE8h É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É †...
  • Page 447 Register Descriptions Synchronous Serial Port Control Register (SSPCR) — I/O Address FFF1h FREE SOFT Receive FIFO buffer status Receive buffer empty. Receive buffer holds data. Transmit FIFO buffer status Transmit buffer empty. Transmit buffer not empty. Emulation/run mode Immediate stop Stop after completion of word Free run Free run...
  • Page 448 Asynchronous Serial Port Control Register (ASPCR) — I/O Address FFF5h FREE SOFT URST Emulation/run mode Immediate stop Process stops after character completion. Free run Free run TX pin level between transmissions TX output forced high TX output forced low Auto-baud alignment Disables auto-baud alignment Enables auto-baud alignment when ADC = 0 Number of stop bits...
  • Page 449 Register Descriptions I/O Status Register (IOSR) — I/O Address FFF6h É É É É É É É É † ‡ Reserved R/W1C Transmit empty indicator ADTR and/or AXSR are full. ADTR and AXSR are empty; ADTR is ready for a new character to transmit. Break interrupt indicator Normal operation Break has been detected on RX pin.
  • Page 450 Instruction Set Comparison This appendix contains a table that compares the TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x instructions alphabetically. Each table entry shows the syntax for the instruction, indicates which devices support the instruction, and describes the operation of the instruction. Section B.1 shows a sample table entry and describes the symbols and abbreviations used in the table.
  • Page 451: B.1 Using The Instruction Set Comparison Table

    2xx refers to the TMS320C2xx devices In this example, you can use the first two syntaxes with TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x devices, but you can use the last syntax only with TMS320C2xx and TMS320C5x devices. The sixth column, Description , briefly describes how the instruction functions.
  • Page 452: Symbols And Acronyms Used In The Instruction Set Summary

    B.1.2 Symbols and Acronyms Used in the Table The following table lists the instruction set symbols and acronyms used throughout this chapter: Table B–1. Symbols and Acronyms Used in the Instruction Set Summary Symbol Description 16-bit immediate value 8-bit immediate value {ind} indirect address accumulator...
  • Page 453 Using the Instruction Set Comparison Table Based on the device, this is how the indirect addressing operand {ind} is interpreted: {ind} where the possible options are separated by vertical bars (|). For example: ADD { ind } is interpreted as: ’C1x devices ’C2x devices ’C2xx devices...
  • Page 454: B.2 Enhanced Instructions

    ADDH is assembled for the ’C2xx or ’C5x, ADDH is replaced by an ADD instruction that performs the same function. These enhanced instructions are valid for TMS320C2x, TMS320C2xx, and TMS320C5x devices (not TMS320C1x). Table B–2 below summarizes the enhanced instructions and the functions that the enhanced instructions perform (based on TMS320C1x/2x mnemonics).
  • Page 455: B.3 Instruction Set Comparison Table

    During shifting, low- order bits are zero filled, and high-order bits are sign extended. TMS320C2xx and TMS320C5x devices: Add the con- tents of the addressed data-memory location or an im- mediate value to the accumulator; if a shift is specified, left shift the data before the add.
  • Page 456 During shifting, low-order bits are zero filled, and high-order bits are sign ex- tended if SXM = 1. TMS320C2xx and TMS320C5x devices: If the result of the addition generates a carry from the accumulator’s MSB, the carry bit is set to 1.
  • Page 457 16 LSBs of the accumulator. The 16 MSBs of the accu- mulator are ANDed with 0s. TMS320C2xx and TMS320C5x devices: AND the con- tents of the addressed data-memory location or a 16-bit immediate value with the contents of the accu- mulator.
  • Page 458 (TMS320C1x) or the contents of the entire cur- rent auxiliary register (TMS320C2x) are 0, branch to the specified program-memory address. TMS320C2x and TMS320C2xx devices: Modify the current AR and ARP (if specified) or decrement the current AR (default). TMS320C1x devices: Decrement the current AR.
  • Page 459 If the TC bit = 1, branch to the specified program- memory address. TMS320C2x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: If the –p port- ing switch is used, modify the current AR and ARP as specified. Branch on Bit = Zero If the TC bit = 0, branch to the specified program- memory address.
  • Page 460 If the contents of the accumulator specified program-memory address. TMS320C2x devices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: Modify the current AR and ARP as specified when the –p porting switch is used. Branch if Accumulator > Zero If the contents of the accumulator are >...
  • Page 461 , and the des- tination block of data memory is pointed to by dst . TMS320C2xx devices: The word of the source and/or the destination space can be pointed to with a long im- mediate value or a data-memory address.
  • Page 462 . TMS320C2xx devices: The word of the source space can be pointed to with a long immediate value. You can use the RPT instruction with BLPD to move consecu- tive words that are pointed at indirectly in data memory to a contiguous program-memory space.
  • Page 463 If the OV flag is set, branch to the specified program- memory address and clear the OV flag. TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: To modify the AR and ARP, use the –p porting switch. Description Zero...
  • Page 464 TMS320C2x, TMS320C2xx and TMS320C5x de- vices: Modify the current AR and ARP as specified. TMS320C2xx and TMS320C5x devices: To modify the AR and ARP, use the –p porting switch. Call Subroutine Indirect The contents of the accumulator specify the address of a subroutine.
  • Page 465 Instruction Set Comparison Table Syntax pma, cond [ , cond ] [, ...] CC[ D ] pma , cond [ , cond ] [, ...] CLRC control bit CMPL CMPR CM CNFD B-16 Call Conditionally If the specified conditions are met, control is passed to the pma.
  • Page 466 Copy the contents of the addressed data-memory lo- cation into the next higher address. DMOV moves data only within on-chip RAM blocks. TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: The on-chip RAM blocks are B0 (when config- ured as data memory), B1, and B2.
  • Page 467 I/O access, and the STRB, R/W, and READY tim- ings are the same as for an external data-memory read. TMS320C2xx and TMS320C5x devices: The IS line goes low to indicate an I/O access, and the STRB, RD, and READY timings are the same as for an external data-memory read.
  • Page 468 LSBs of the accumulator. The MSBs of the accumula- tor are zeroed. The data is treated as a 16-bit unsigned number. TMS320C2xx: A constant of 0 clears the contents of the accumulator to 0 with no sign extension. TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison...
  • Page 469 TMS320C1x and TMS320C2x devices: Load the con- tents of the addressed data-memory location into the designated auxiliary register. TMS320C25, TMS320C2xx, and TMS320C5x de- vices: Load the contents of the addressed data- memory location or an 8-bit or 16-bit immediate value into the designated auxiliary register.
  • Page 470 All high-order bits are ignored. DP = 0 defines page 0 (words 0–127), and DP = 1 defines page 1 (words 128–143/255). TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: Load the 9 LSBs of the addressed data-memory location or a 9-bit immediate value into the DP register.
  • Page 471 T register (TMS320C1x/2x/2xx) or TREG0 (TMS320C5x) and add the contents of the P register to the accumulator. TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: Before the add, shift the contents of the P regis- ter as specified by the PM status bits.
  • Page 472 P register. TMS320C2xx and TMS320C5x devices: Multiply the contents of the T register (TMS320C2xx) or TREG0 (TMS320C5x) by the contents of the addressed data- memory location or a 13-bit or 16-bit immediate value;...
  • Page 473 Instruction Set Comparison Table Syntax MPYA dma MPYA { ind } [ , next ARP ] MPYK 13-bit constant MPYS dma MPYS { ind } [ , next ARP ] MPYU dma MPYU { ind } [ , next ARP ] NORM NORM { ind } OPL [# lk ,] dma...
  • Page 474 LSBs of the accumulator with the contents of the ad- dressed data-memory location. The 16 MSBs of the accumulator are ORed with 0s. TMS320C2xx and TMS320C5x devices: OR the 16 LSBs of the accumulator or a 16-bit immediate value with the contents of the addressed data-memory loca- tion.
  • Page 475 Instruction Set Comparison Table Syntax POPD dma POPD { ind } [ , next ARP ] PSHD dma PSHD { ind } [ , next ARP ] PUSH RET[ D ] RETC cond [ , cond ] [, ...] RETC[ D ] cond [ , cond ] [, ...] B-26...
  • Page 476 Syntax RETE RETI RFSM ROLB RORB ROVM Enable Interrupts and Return From Interrupt Copy the contents of the top of the stack into the PC and pop the stack one level. RETE automatically clears the global interrupt enable bit and pops the shadow registers (stored when the interrupt was tak- en) back into their corresponding strategic registers.
  • Page 477 RPTC; the instruction following RPT is executed the number of times indicated by RPTC + 1. TMS320C2xx and TMS320C5x devices: Load the 8 LSBs of the addressed value or an 8-bit or 16-bit immediate value into the RPTC; the instruction follow- ing RPT is repeated n times, where n is RPTC+1.
  • Page 478: Tms320C209

    A shift value of 0 must be specified if the ARP is to be changed. TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: Store the 16 LSBs of the accumulator into the addressed data-memory location. If a shift is specified, shift the contents of the accumulator before storing.
  • Page 479 Instruction Set Comparison Table Syntax SBBB SBLK # lk [ , shift ] SBRK # k SETC control bit SFLB SFRB SFSM B-30 Subtract ACCB From Accumulator With Borrow Subtract the contents of the ACCB and the logical in- version of the carry bit from the accumulator. The result is stored in the accumulator;...
  • Page 480 Subtract P Register From Accumulator Subtract the contents of the P register from the contents of the accumulator. TMS320C2x, TMS320C2xx, and TMS320C5x de- vices: Before the subtraction, shift the contents of the P register as specified by the PM status bits.
  • Page 481 Instruction Set Comparison Table Syntax SQRA dma SQRA { ind } [ , next ARP ] SQRS dma SQRS { ind } [ , next ARP ] SST dma SST { ind } [ , next ARP ] SST # n, dma SST # n, { ind } [ , next ARP ] SST1 dma SST1 { ind } [ , next ARP ]...
  • Page 482 SXM = 1. TMS320C2xx and TMS320C5x devices: Subtract the contents of the addressed data-memory location or an 8- or 16-bit constant from the accumulator. If a shift is specified, left shift the data before subtracting.
  • Page 483 The TRAP instruction is a software interrupt that trans- fers program control to program-memory address 30h (TMS320C2x) or 22h (TMS320C2xx/5x) and pushes the PC + 1 onto the hardware stack. The instruction at address 30h or 22h may contain a branch instruction to transfer control to the TRAP routine.
  • Page 484 16 LSBs of the accumulator. The MSBs are not af- fected. TMS320C2xx and TMS320C5x devices: Exclusive- OR the contents of the addressed data-memory loca- tion or a 16-bit immediate value with the accumulator.
  • Page 485 Instruction Set Comparison Table Syntax ZALR dma ZALR { ind } [ , next ARP ] ZALS dma ZALS { ind } [ , next ARP ] B-36 Zero Low Accumulator, Load High Accumulator With Rounding Load the contents of the addressed data-memory location into the 16 MSBs of the accumulator.
  • Page 486: Program Examples

    (literature number SPRU024) TMS320C2xx C Source Debugger User’s Guide (literature number SPRU151) For more information about these documents and about ordering them, see Related Documentation From Texas Instruments on page vi of the Preface. Topic About These Program Examples Shared Program Code .
  • Page 487: C.1 About These Program Examples

    About These Program Examples About These Program Examples C.1 About These Program Examples Figure C–1 illustrates the basic process for creating assembly language files and then generating executable files from them: 1) Use the ’C2xx assembler to create: 2) Assemble the program. The command shown under Step 2 in the figure generates an object file and a file containing a listing of assembler errors encountered.
  • Page 488: Shared Programs In This Appendix

    The program examples in Section C.2 and Section C.3 consist of code for shared files and task-specific files. Table C–1 describes the shared programs. Shared files contain code that is used by multiple task-specific files. The task- specific programs are described in Table C–2. Every task-specific file that uses the header files includes them by way of the .copy assembler directive: .copy ”init.h”...
  • Page 489 About These Program Examples Table C–2. Task-Specific Programs in This Appendix (Continued) Program Functional Description uart.asm Causes the asynchronous serial port to transmit a test message continuously at 1200 baud. Baud rate is 1200 at 50-ns cycle time. echo.asm Echoes the character received by the asynchronous serial port at 1200 baud autobaud.asm Causes the asynchronous serial port to lock on to the incoming...
  • Page 490: C.2 Shared Program Code

    C.2 Shared Program Code Example C–1. Generic Command File (c203.cmd) /* Title: c203.cmd /* Generic command file for linking TMS320C2xx assembler files */ /* input files: *.obj files /* output files: *.out file /* Map files: *.map file (optional) /* TMS320C2xx architecture declaration for linker use MEMORY PAGE 0: /* PM –...
  • Page 491: C–2 Header File With I/O Register Declarations (Init.h)

    Shared Program Code Example C–2. Header File With I/O Register Declarations (init.h) * File: init.h * * Include file with I/O register declarations * .mmregs .bss dmem,10 .def ini_d, start,codtx ini_d: .usect ”new”,10 .data .word 055aah .word 0aa55h * On–chip register equates * CLKOUT clk1 .set...
  • Page 492: C–3 Header File With Interrupt Vector Declarations (Vector.h)

    Example C–3. Header File With Interrupt Vector Declarations (vector.h) * File: vector.h * File defines Interrupt vector labels .sect ”vectors” start inpt1 inpt23 timer codrx codtx uart .space 45*16 .word 1,2,3,4,5 ; reset vector – Jump to label start on reset ;...
  • Page 493: C.3 Task-Specific Program Code

    Task-Specific Program Code C.3 Task-Specific Program Code Example C–4. Implementing Simple Delay Loops (delay.asm) * File: delay.asm * Function: Delay loop. XF and I/O 3 pins toggle after each delay .title ”Delay routine” ; Title .copy ”init.h” .copy ”vector.h” .text start: clrc setc...
  • Page 494: C–5 Testing And Using The Timer (Timer.asm)

    Example C–5. Testing and Using the Timer (timer.asm) * File: timer.asm * Function: Timer test code * PRD=0x00ff,TDDR=f @ 50ns, gives an interrupt interval=205us * PRD=0xffff,TDDR=0 @ 50ns, gives an interrupt interval=3.27ms* * Timer interval measurable on I/O 2,3 or xf pins .title ”Timer Test”...
  • Page 495: C–6 Testing And Using Interrupt Int1 (Intr1.Asm)

    Task-Specific Program Code Example C–6. Testing and Using Interrupt INT1 (intr1.asm) * File: intr1.asm * Function: Interrupt test code * For each INT1 interrupt XF,I/O pins IO3 and IO2 will toggle and * * transmit char ’c’ through UART .title ”Interrupt 1 Test” .copy ”init.h”...
  • Page 496: C–7 Implementing A Hold Operation (Hold.asm)

    Example C–7. Implementing a HOLD Operation (hold.asm) * File: hold.asm * Function: HOLD test code * Check for HOLDA toggle for HOLD requests in MODE 0 * Check for XF toggle on HOLD/INT1 requests in MODE 1 .title ” HOLD Test ” .mmregs .set 0FFECh...
  • Page 497: C–8 Testing And Using Interrupts Int2 And Int3 (Intr23.Asm)

    Task-Specific Program Code Example C–8. Testing and Using Interrupts INT2 and INT3 (intr23.asm) * File: intr23.asm * Function: Interrupt test code * Interrupt on INT2 or INT3 will toggle IO3 and IO2 bits * and icr value copied in the Buffer @300 .title ”...
  • Page 498: C–9 Asynchronous Serial Port Transmission (Uart.asm)

    Example C–9. Asynchronous Serial Port Transmission (uart.asm) * File: uart.asm * Function: UART Test Code * Continuously sends ’’C203 UART is fine’ at 1200 baud. .title ” UART Test” .copy ”init.h” .copy ”vector.h” .text start: clrc setc INTM * UART initialization * splk #0ffffh,ifr splk...
  • Page 499: C–10 Loopback To Verify Transmissions Of Asynchronous Serial Port (Echo.asm)

    Task-Specific Program Code Example C–9. Asynchronous Serial Port Transmission (uart.asm) (Continued) ar1,#rxbuf ar0, #20 *,ar1 clrc intm wait: clrc idle wait uart: setc splk #0ffffh,67h *+,adtr *,ar0 banz skip,ar1 ar1,#rxbuf ar0,#20 skip: splk #0020h,ifr clrc intm inpt1: inpt23: timer: codtx: codrx: .end Example C–10.
  • Page 500 Example C–10. Loopback to Verify Transmissions of Asynchronous Serial Port (echo.asm) (Continued) * UART initialization * splk #0ffffh,ifr splk #0000h,60h 60h, wsgr splk #0c080h,61h 61h, aspcr splk #0e080h,61h 61h,aspcr splk #4fffh,62h 62h,iosr splk #0411h, 63h 63h, brd splk #20h,imr *,ar1 * Load data at DM300 ar1,#rxbuf ar0, #size...
  • Page 501: C–11 Testing And Using Automatic Baud-Rate Detection On Asynchronous Serial Port (Autobaud.asm)

    Task-Specific Program Code Example C–11. Testing and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) * File: autobaud.asm * Function: UART,auto baud test Locks to incoming baud rate if the first character is ”A” or ”a” & continuously echoes data received through the port.
  • Page 502 Example C–11. Testing and Using Automatic Baud-Rate Detection on Asynchronous Serial Port (autobaud.asm) (Continued) uart: setc 68h,iosr 68h,1 bcnd rcv,ntc splk #4fffh,67h 67h,iosr splk #0e080h,67h 67h, aspcr rcv: 68h,iosr 68h,7 bcnd skip,ntc *,adtr *+,adtr *,ar0 banz skip,ar1 ar1,#rxbuf ar0,#size skip: splk #0020h,ifr clrc...
  • Page 503: C–12 Testing And Using Asynchronous Serial Port Delta Interrupts (Bitio.asm)

    Task-Specific Program Code Example C–12. Testing and Using Asynchronous Serial Port Delta Interrupts (bitio.asm) * File: bitio.asm * Function: Delta interrupt Accepts delta interrupt on IO pins 3 and 2 If bit level changes on bit 7, send character ’c’ through UART &...
  • Page 504 Example C–12. Testing and Using Asynchronous Serial Port Delta Interrupts(bitio.asm) (Continued) uart: setc 68h,iosr 68h,8 bcnd poll,ntc clrc 65h, adtr splk #0080h,6bh 6bh,iosr clrc splk #20h,ifr clrc intm poll: 68h,iosr 68h,9 bcnd poll1,ntc clrc 67h, adtr splk #0040h,6bh 6bh,iosr poll1: clrc splk #20h,ifr...
  • Page 505: C–13 Synchronous Serial Port Continuous Mode Transmission (Ssp.asm)

    Task-Specific Program Code Example C–13. Synchronous Serial Port Continuous Mode Transmission (ssp.asm) * File: ssp.asm * Function: Continuous transmit in CONTINUOUS mode Internal shift clock and frame sync Transmit FIFO level is set to 4 .title ”SSP Continuous mode” .copy ”init.h” .copy ”vector.h”...
  • Page 506: C–14 Using Synchronous Serial Port With Codec Device (Ad55.Asm)

    Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) * File: ad55.asm * Function: Burst mode simple loop back on AD55 CODEC CODEC master clock 10 MHz Simple I/O at 9.6-kHz sampling .title ”AD55 codec simple I/O” ; Title .copy ”init.h”...
  • Page 507 Task-Specific Program Code Example C–14. Using Synchronous Serial Port With Codec Device (ad55.asm) (Continued) codtx: splk #0010h, ifr clrc intm codrx: setc *,sdtr lacc *+,0 #0fffeh,0 sacl 6ah,0 6ah,sdtr *,ar0 banz skip,ar1 ar1,#rxbuf ar0,#size skip: splk #0008h, ifr clrc intm inpt1: inpt23: timer:...
  • Page 508: C.4 Introduction To Generating Boot Loader Code

    The ’C2xx on-chip boot loader boots software from an 8-bit external EPROM to a 16-bit external RAM at reset. This section introduces to the procedure for using Texas Instruments development tools to generate the code that will be loaded into the EPROM.
  • Page 509: C–15 Linker Command File

    Introduction to Generating Boot Loader Code Example C–15. Linker Command File MEMORY PAGE 0: /* PM – Program memory EX1_PM :ORIGIN=0H B0_PM :ORIGIN=0FF00H, LENGTH=0100H /* BLOCK MAP IN CNF=1 */ PAGE 1: /* DM – Data memory REGS :ORIGIN=0H BLK_B2 :ORIGIN=60H BLK_B0 :ORIGIN=200H ,...
  • Page 510 The size of a printed circuit board is a consideration in many DSP applications. To make full use of the board space, Texas Instruments offers this ROM code option that reduces the chip count and provides a single-chip solution. This op-...
  • Page 511: Tms320 Rom Code Submittal Flow Chart

    — TMS320 New Code Release Form — Print Evaluation and Acceptance Form (PEAF) — Purchase order for mask prototypes — TMS320 code Texas Instruments responds: — Customer code input into TI system — Code sent back to customer for verification Customer TMS320 Design...
  • Page 512 Any masked ROM device may be resymbolized as TI standard product and resold as though it were an unprogrammed version of the device, at the convenience of Texas Instruments. The use of the ROM-protect feature does not hold for this release statement.
  • Page 513 Design Considerations for Using XDS510 Emulator This appendix assists you in meeting the design requirements of the Texas Instruments XDS510 emulator with respect to IEEE-1149.1 designs and discusses the XDS510 cable (manufacturing part number 2617698-0001). This cable is identified by a label on the cable pod marked JTAG 3/5V and sup- ports both standard 3-V and 5-V target system power inputs.
  • Page 514: E.1 Designing Your Target System's Emulator Connector (14-Pin Header)

    Designing Your Target System’s Emulator Connector (14-Pin Header) E.1 Designing Your Target System’s Emulator Connector (14-Pin Header) JTAG target devices support emulation through a dedicated emulation port. This port is accessed directly by the emulator and provides emulation func- tions that are a superset of those specified by IEEE 1149.1. To communicate with the emulator, your target system must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure E–1.
  • Page 515: E–1 14-Pin Header Signal Descriptions

    Table E–1. 14-Pin Header Signal Descriptions Signal EMU0 EMU1 PD(V TCK_RET TRST † I = input; O = output ‡ Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed.
  • Page 516: E.2 Bus Protocol

    Bus Protocol E.2 Bus Protocol The IEEE 1149.1 specification covers the requirements for the test access port (TAP) bus slave devices and provides certain rules, summarized as follows: The TMS and TDI inputs are sampled on the rising edge of the TCK signal of the device.
  • Page 517: Emulator Cable Pod Interface

    E.3 Emulator Cable Pod Figure E–2 shows a portion of the emulator cable pod. The functional features of the pod are: TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By default, these signals are not terminated. TCK is driven with a 74LVT240 device.
  • Page 518: Emulator Cable Pod Timings

    These timing parame- ters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only. Texas Instruments does not test or guarantee these timings.
  • Page 519: E.5 Emulation Timing Calculations

    E.5 Emulation Timing Calculations Example E–1 and Example E–2 help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate data sheet for the device you are emulating. The examples use the following assumptions: Also, the examples use the following values from Table E–2 on page E-6: There are two key timing paths to consider in the emulation design: The TCK_RET-to-TMS or TDI path, called t tion delay time)
  • Page 520: E–1 Key Timing For A Single-Processor System Without Buffers

    Emulation Timing Calculations Example E–1. Key Timing for a Single-Processor System Without Buffers In this case, because the TCK_RET-to-TMS/TDI path requires more time to complete, it is the limiting factor. Example E–2. Key Timing for a Single- or Multiple-Processor System With Buffered Input and Output In this case also, because the TCK_RET-to-TMS/TDI path requires more time to complete, it is the limiting factor.
  • Page 521: Emulation Timing Calculations

    In a multiprocessor application, it is necessary to ensure that the EMU0 and EMU1 lines can go from a logic low level to a logic high level in less than 10 s, this parameter is called rise time, t = 5(R pullup = 5(4.7 k = 5(4.7...
  • Page 522: Emulator Connections Without Signal Buffering

    Connections Between the Emulator and the Target System E.6 Connections Between the Emulator and the Target System It is extremely important to provide high-quality signals between the emulator and the JTAG target system. You must supply the correct signal buffering, test clock inputs, and multiple processor interconnections to ensure proper emula- tor and target system operation.
  • Page 523: Emulator Connections With Signal Buffering

    Figure E–5. Emulator Connections With Signal Buffering The EMU0 and EMU1 signals must have pullup resistors connected to V provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications. The input buffers for TMS and TDI should have pullup resistors connected to nected.
  • Page 524: E.6.2 Using A Target-System Clock

    Connections Between the Emulator and the Target System E.6.2 Using a Target-System Clock Figure E–6 shows an application with the system test clock generated in the target system. In this application, the emulator’s TCK signal is left uncon- nected. Figure E–6. Target-System-Generated Test Clock System test clock Note: There are two benefits in generating the test clock in the target system:...
  • Page 525: Multiprocessor Connections

    E.6.3 Configuring Multiple Processors Figure E–7 shows a typical daisy-chained multiprocessor configuration that meets the minimum requirements of the IEEE 1149.1 specification. The emulation signals are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system. One of the benefits of this interface is that you can slow down the test clock to eliminate timing problems.
  • Page 526: Pod/Connector Dimensions

    Physical Dimensions for the 14-Pin Emulator Connector E.7 Physical Dimensions for the 14-Pin Emulator Connector The JTAG emulator target cable consists of a 3-foot section of jacketed cable that connects to the emulator, an active cable pod, and a short section of jack- eted cable that connects to the target system.
  • Page 527: E–9 14-Pin Connector Dimensions

    Figure E–9. 14-Pin Connector Dimensions Physical Dimensions for the 14-Pin Emulator Connector Cable Connector, side view 0.100 inch, nominal (pin spacing) Cable 2 rows of pins Design Considerations for Using XDS510 Emulator 0.20 i nch, nominal 0.66 inch, nominal Key, pin 6 0.87 inch, nominal 0.100 inch,...
  • Page 528: Emulation Design Considerations

    Emulation Design Considerations E.8 Emulation Design Considerations This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JTAG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors.
  • Page 529: Connecting A Secondary Jtag Scan Path To A Scan Path Linker

    Figure E–10. Connecting a Secondary JTAG Scan Path to a Scan Path Linker The TRST signal from the main scan path drives all devices, even those on the secondary scan paths of the SPL. The TCK signal on each target device on the secondary scan path of an SPL is driven by the SPL’s DTCK signal.
  • Page 530: E.8.2 Emulation Timing Calculations For A Scan Path Linker (Spl)

    Emulation Design Considerations E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) Example E–3 and Example E–4 help you to calculate the key emulation tim- ings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheet for your target device.
  • Page 531: E–3 Key Timing For A Single-Processor System Without Buffering (Spl)

    Of the following two cases, the worst-case path delay is calculated to deter- mine the maximum system test clock frequency. Example E–3. Key Timing for a Single-Processor System Without Buffering (SPL) In this case, the TCK-to-DTMS/DTDL path is the limiting factor. Example E–4.
  • Page 532: E.8.3 Using Emulation Pins

    Emulation Design Considerations E.8.3 Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, 3-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they provide one of two types of output: Signal Event.
  • Page 533: Emu0/1 Configuration To Meet Timing Requirements Of Less Than 25 Ns

    Figure E–11. EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns Backplane XCNT_ENABLE EMU0/1-IN EMU0/1-OUT To emulator EMU0 Notes: 1) The low time on EMU0/1-IN should be at least one TCK cycle and less than 10 pin to a high state. 2) To enable the open-collector driver and pullup resistor on EMU1 to provide rise/fall times of less than 25 ns, the modifi- cation shown in this figure is suggested.
  • Page 534: Suggested Timings For The Emu0 And Emu1 Signals

    Emulation Design Considerations The bused EMU0/1 signals go into a programmable logic array device when a low level is detected on the EMU0/1-OUT signal. This pulse must be longer than one TCK period to affect the devices but less than 10 s to avoid possible conflicts or retriggering once the emulation software clears the device’s pins.
  • Page 535: Emu0/1 Configuration With Additional And Gate To Meet

    Figure E–13. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements of Greater Than 25 ns Backplane XCNT_ENABLE EMU0/1-IN EMU0/1-OUT To Emulator EMU0 Circuitry required for >25-ns rise/fall time modification To emulator EMU1 Notes: 1) The low time on EMU0/1-IN should be at least one TCK cycle and less than 10 port to a high state.
  • Page 536: E.8.4 Performing Diagnostic Applications

    For systems that require built-in diagnostics, it is possible to connect the emulation scan path directly to a TI ACT8990 test bus controller (TBC) instead of the emulation header. The TBC is described in the Texas Instruments Advanced Logic and Bus Interface Logic Data Book . Figure E–15 shows the scan path connections of n devices to the TBC.
  • Page 537: Tbc Emulation Connections For N Jtag Scan Paths

    Figure E–15. TBC Emulation Connections for n JTAG Scan Paths TMS2/EVNT0 TMS3/EVNT1 TMS4/EVNT2 TMS5/EVNT3 In the system design shown in Figure E–15, the TBC emulation signals TCKI, TDO, TMS0, TMS2/EVNT0, TMS3/EVNT1, TMS5/EVNT3, TCKO, and TDI0 are used, and TMS1, TMS4/EVNT2, and TDI1 are not connected. The target devices’...
  • Page 538 A0–A15: Collectively, the external address bus; the 16 pins are used in par- allel to address external data memory, program memory, or I/O space. ACC: See accumulator. ACCH: Accumulator high word. The upper 16 bits of the accumulator. See also accumulator . ACCL: Accumulator low word.
  • Page 539 Glossary analog-to-digital (A/D) converter: A circuit that translates an analog signal AR: See auxiliary register . AR0–AR7: Auxiliary registers 0 through 7. See auxiliary register . ARAU: See auxiliary register arithmetic unit (ARAU). ARB: See auxiliary register pointer buffer (ARB) . ARP: ARSR: Asynchronous serial port receive shift register.
  • Page 540 B0: An on-chip block of dual-access RAM that can be configured as either data memory or program memory, depending on the value of the CNF bit in status register ST1. B1: An on-chip block of dual-access RAM available for data memory. B2: An on-chip block of dual-access RAM available for data memory.
  • Page 541 Glossary CALU: See central arithmetic logic unit (CALU). carry bit: Bit 9 of status register ST1; used by the CALU for extended central arithmetic logic unit (CALU): The 32-bit wide main arithmetic logic CIO0–CIO3 bits: Bits 0–3 of the asynchronous serial port control register CLK register: CLKOUT1-pin control register.
  • Page 542 clock mode (clock generator): One of the modes which sets the internal CPU clock frequency to a fraction or multiple of the frequency of the input clock signal CLKIN. The ’C209 has two clock modes ( 2 and 2); other ’C2xx devices have four clock modes ( 2, 1, 2, and 4).
  • Page 543 Glossary current data page: The data page indicated by the content of the data page D0–D15: Collectively, the external data bus; the 16 pins are used in parallel DARAM: Dual-access RAM . RAM that can be accessed twice in a single DARAM configuration bit (CNF): data-address generation logic: Logic circuitry that generates the address- data page: One block of 128 words in data memory.
  • Page 544 decode phase: The phase of the pipeline in which the instruction is de- coded. See also pipeline ; instruction-fetch phase ; operand-fetch phase; instruction-execute phase . delta interrupt: An asynchronous serial port interrupt (TXRXINT) that is generated if a change takes place on one of these general-purpose I/O pins: IO0, IO1, IO2, or IO3.
  • Page 545 Glossary DRAB: See data-read address bus (DRAB). DRDB: See data read bus (DRDB). DS: Data memory select pin . The ’C2xx asserts DS to indicate an access to DSWS: Data-space wait-state bit(s). A value in the wait-state generator con- dual-access RAM: See DARAM . dummy cycle: A CPU cycle in which the CPU intentionally reloads the pro- DWAB: See data-write address bus (DWAB).
  • Page 546 FR0/FR1: FIFO receive-interrupt bits . Bits 8 and 9 of the synchronous serial port control register (SSPCR); together they set an interrupt trigger condition based on the number of words in the receive FIFO buffer. frame synchronization (frame sync) mode: One of two modes in the syn- chronous serial port that determine whether frame synchronization pulses are necessary between consecutive data transfers.
  • Page 547 Glossary general-purpose input/output pins: Pins that can be used to accept input global data space: One of the four ’C2xx address spaces. The global data GREG: Global memory allocation register . A memory-mapped register hardware interrupt: An interrupt triggered through physical connections HOLD: An input signal that allows external devices to request control of the HOLDA: HOLD acknowledge signal .
  • Page 548 IC: (Used in earlier documentation.) See interrupt control register (ICR). ICR: See interrupt control register (ICR) . IFR: See interrupt flag register (IFR) . immediate addressing: One of the methods for obtaining data values used by an instruction; the data value is a constant embedded directly into the instruction word;...
  • Page 549 Glossary INT1–INT3: Three external pins used to generate general-purpose hard- internal interrupt: A hardware interrupt caused by an on-chip peripheral. interrupt: A signal sent to the CPU that (when not masked or disabled) interrupt acknowledge signal (IACK): interrupt control register (ICR): A 16-bit register used to differentiate interrupt flag register (IFR): interrupt latency: interrupt mask register (IMR): A 16-bit memory-mapped register used to...
  • Page 550 IO0–IO3 bits: Bits 0–3 of the IOSR. When pins IO0–IO3 are configured as inputs, these bits reflect the current logic levels on the pins. For example, the IO0 bit reflects the level on the IO0 pin. See also CIO0–CIO3 bits ; DIO0–DIO3 bits .
  • Page 551 Glossary Glossary LSB: Least significant bit. The lowest order bit in a word. When used in plural machine cycle: See CPU cycle . maskable interrupt: A hardware interrupt that can be enabled or disabled master clock output signal: See CLKOUT1 . master phase: See logic phase .
  • Page 552 MSTACK: See micro stack . multiplier: A part of the CPU that performs 16-bit 16-bit multiplication and generates a 32-bit product. The multiplier operates using either signed or unsigned 2s-complement arithmetic. next AR: See next auxiliary register . next auxiliary register: The register that will be pointed to by the auxiliary register pointer (ARP) when an instruction that modifies ARP is finished executing.
  • Page 553 Glossary Glossary OV bit: Overflow flag bit. Bit 12 of status register ST0; indicates whether the overflow (in a register): A condition in which the result of an arithmetic op- overflow (in the synchronous serial port): A condition in which the re- overflow mode: The mode in which an overflow in the accumulator will overrun: A condition in the receiver of the asynchronous serial port.
  • Page 554 pipeline: A method of executing instructions in an assembly line fashion. The ’C2xx pipeline has four independent phases. During a given CPU cycle, four different instructions can be active, each at a different stage of completion. See also instruction-fetch phase ; instruction-decode phase ;...
  • Page 555 Glossary program control logic: Logic circuitry that decodes instructions, manages program counter (PC): A register that indicates the location of the next program read bus (PRDB): A 16-bit internal bus that carries instruction PS: Program select pin . The ’C2xx asserts PS to indicate an access to exter- PSC: Timer prescaler counter .
  • Page 556 receive interrupt (asynchronous serial port): An interrupt (TXRXINT) caused during reception by any one of these events: the ADTR holds a new character; overrun occurs; a framing error occurs; a break has been detected on the RX pin; a character A or a has been detected in the ADTR by the automatic baud-rate detection logic.
  • Page 557 Glossary RPTC: See repeat counter (RPTC). RRST: Receive reset bit . Bit 4 of the synchronous serial port control register RS: Reset pin . When driven low, causes a reset on any ’C2xx device, includ- RS: Reset pin . (On the ’C209 only) When driven high, causes a reset. RSR: Receive shift register.
  • Page 558 single-access RAM: See SARAM . slave phase: See latch phase . SOFT bit (asynchronous serial port): Bit 14 in the asynchronous serial port control register (ASPCR); a special emulation bit that is used in con- junction with bit 15 (FREE) to determine the state of an asynchronous serial port transfer when a software breakpoint is encountered during emulation.
  • Page 559 Glossary status registers ST0 and ST1: Two 16-bit registers that contain bits for de- STB bit: Stop bit selector . Bit 6 of the asynchronous serial port control regis- stop bit: Every 8-bit data value transmitted or received by the asynchronous STRB: External access active strobe .
  • Page 560 TIM bit: Transmit interrupt mask bit . Bit 8 of the asynchronous serial port control register (ASPCR); enables or disables transmit interrupts of the asynchronous serial port. TIM register: See timer counter register (TIM) . timer counter register (TIM): A 16-bit memory-mapped register that holds the main count for the on-chip timer.
  • Page 561 Glossary transmit mode (TXM) bit: Bit 3 of the synchronous serial port control regis- transmit pin (asynchronous serial port): See TX pin . transmit pin (synchronous serial port): See DX pin . transmit/receive interrupt (TXRXINT): transmit register (asynchronous serial port): transmit register (synchronous serial port): See SDTR .
  • Page 562 URST: Reset asynchronous serial port bit . Bit 13 of the asynchronous serial port control register (ASPCR); resets the asynchronous port. vector: See interrupt vector . vector location: See interrupt vector location . wait state: A CLKOUT1 cycle during which the CPU waits when reading from or writing to slower external memory.
  • Page 563 Glossary zero fill: Fill the unused low or high order bits in a register with zeros. F-26...
  • Page 564 * operand 6-10 *+ operand 6-10 *– operand 6-10 *0+ operand 6-10 *0– operand 6-10 *BR0+ operand 6-11 *BR0– operand 6-11 14-pin connector, dimensions E-15 14-pin header header signals E-2 JTAG E-2 4-level pipeline operation 5-7 A0–A15 (external address bus) definition 4-3 shown in figure 4-6, 4-10, 4-13, 4-15, 4-26 ABS instruction 7-21...
  • Page 565 Index accumulator instructions (continued) store high byte of accumulator to data memory (SACH) 7-148 store low byte of accumulator to data memory (SACL) 7-150 subtract conditionally from accumulator (SUBC) 7-180 subtract PREG from accumulator (SPAC) 7-160 subtract PREG from accumulator and load TREG (LTS) 7-100 subtract PREG from accumulator and multiply (MPYS) 7-118...
  • Page 566 asynchronous serial port (continued) baud-rate detection logic detecting A or a character (ADC bit) 10-10 enabling/disabling (CAD bit) 10-8 block diagram 10-3 components 10-3 configuration 10-7 delta interrupts 10-17 enabling/disabling (DIM bit) 10-8 emulation modes (FREE and SOFT bits) 10-7 features 10-1 interrupts (TXRXINTs) flag bit (TXRXINT) 5-21...
  • Page 567 Index B instruction 7-39 BACC instruction 7-40 BANZ instruction 7-41 baud-rate detection procedure 10-14 divisor register (BRD) 10-13 generator 10-4 BCND instruction 7-43 BI bit 10-10 BIO pin 8-17 to 8-18 BIT instruction 7-45 bit-reversed indexed addressing 6-10, F-3 BITT instruction 7-47 BLDD instruction 7-49 block diagrams ’C2xx overall 2-2...
  • Page 568 bus request pin (BR) definition 4-3 shown in figure 4-13, 4-15 buses block diagram 2-4 data read bus (DRDB) 2-3 data write bus (DWEB) 2-3 data-read address bus (DRAB) 2-3 data-write address bus (DWAB) 2-3 program address bus (PAB) definition 2-3 used in program-memory address genera- tion 5-3 program read bus (PRDB) 2-3...
  • Page 569 Index CMPR instruction 7-65 CNF (DARAM configuration bit) 3-16 code compatibility 1-6 codec, definition F-5 conditional instructions 5-10 to 5-13 conditional branch 5-11 to 5-13 conditional call 5-12 to 5-13 conditional return 5-12 to 5-13 conditions that may be tested 5-10 stabilization of conditions 5-11 using multiple conditions 5-10 configuration...
  • Page 570 data memory select pin (DS) definition 4-3 shown in figure 4-10, 4-13 data page 0 4-8 caution about test/emulation addresses 4-8 data page pointer (DP) caution about initializing DP 6-5 definition 3-16 load (LDP instruction) 7-83 role in direct addressing 6-4 data read bus (DRDB) 2-3 data write bus (DWEB) 2-3 data-read address bus (DRAB) 2-3...
  • Page 571 Index emulator cable pod E-5 connection to target system, JTAG mechanical dimensions E-14 to E-25 designing the JTAG cable E-1 emulation pins E-20 pod interface E-5 pod timings E-6 signal buffering E-10 to E-13 target cable, header design E-2 to E-3 enhanced instructions B-5 error conditions asynchronous serial port...
  • Page 572 hardware interrupts definition 5-15 nonmaskable external 5-27 priorities 5-16 types 5-15 hardware reset 5-33 header 14-pin E-2 dimensions, 14-pin E-2 HOLD (HOLD operation request pin) definition 4-4 use in HOLD operation 4-27 HOLD acknowledge pin (HOLDA) definition 4-4 use in HOLD operation 4-27 HOLD operation description 4-27 during reset 4-29...
  • Page 573 Index IMR (interrupt mask register) 5-22 to 5-38 bits ’C203/C204 5-23 ’C209 11-13 in interrupt acknowledgement process 5-19 quick reference A-7 IN instruction 7-69 IN0 bit 9-10 indirect addressing description 6-9 effects on auxiliary register pointer (ARP) 6-14 to 6-16 effects on current auxiliary register 6-14 to 6-16 examples 6-15 modifying auxiliary register content 6-17...
  • Page 574 INT1 interrupt ’C203/C204 flag bit (HOLD/INT1) 5-22 mask bit (HOLD/INT1) 5-24 priority 5-16 vector location 5-16 ’C209 flag bit 11-12 mask bit 11-13 priority 11-10 vector location 11-10 INT2 bit (’C209) in interrupt flag register (IFR) 11-12 in interrupt mask register (IMR) 11-13 INT2 interrupt ’C203/C204 flag bits...
  • Page 575 5-27 operand (K) values ’C203/C204 5-16 ’C209 11-10 introduction TMS320 devices 1-2 TMS320C2xx devices 1-5 IO0–IO3 (bits) 10-13 reading current logic level on pins IO0–IO3 10-16 IO0–IO3 (pins) 10-15 to 10-17 IOSR (I/O status register) detecting change on pins IO0–IO3 10-16...
  • Page 576 See also I/O space address map ’C203 4-32 ’C204 4-35 ’C209 11-6 data page 0 4-8 available on TMS320C2xx devices 2-7 available types 1-6 boot loader 4-14 boot source (EPROM) 4-14 diagram 4-14 enabling 4-17 execution 4-18 generating code for EPROM C-23 to C-24...
  • Page 577 Index memory (continued) introduction 4-2 local data memory description 4-7 to 4-10 pages of (diagram) 4-7 on-chip memory, advantages 4-2 organization 4-2 overview 2-7 pins for external interfacing 4-3 program memory 4-5 to 4-6 address generation logic 5-2 address sources 5-3 RAM (dual-access) configuration ’C203 4-33...
  • Page 578 next program address register (NPAR) definition F-15 shown in figure 5-2 NMI hardware interrupt description 5-27 priority ’C203/C204 5-17 ’C209 11-11 vector location ’C203/C204 5-17 ’C209 11-11 NMI instruction 7-124 introduction 5-28 vector location ’C203/C204 5-17 ’C209 11-11 nonmaskable interrupts 5-27 definition 5-15 flow chart of operation 5-29 hardware-initiated 5-27...
  • Page 579 Index OUT instruction 7-132 output modes external count E-20 signal event E-20 output shifter 3-11 OV (overflow flag bit) 3-16 overflow in accumulator detecting (OV bit) 3-16 enabling/disabling overflow mode (OVM bit) 3-17 overflow in synchronous serial port burst mode 9-29 continuous mode 9-30 detecting (OVF bit) 9-10 overflow mode bit (OVM) 3-17...
  • Page 580 PREG instructions (continued) load high bits of PREG (LPH) 7-85 set PREG output shift mode (SPM) 7-167 store high word of PREG to data memory (SPH) 7-161 store low word of PREG to data memory (SPL) 7-163 store PREG to accumulator (PAC instruc- tion) 7-134 store PREG to accumulator and load TREG (LTP) 7-98...
  • Page 581 Index program memory (continued) configuration RAM (dual-access) ’C203 4-33 ’C204 4-36 ’C209 11-8 RAM (single-access) 11-7 ’C204 4-36 ’C209 11-7 description 4-5 external interfacing 4-5 caution about proper timing 4-5 program memory select pin (PS) definition 4-3 shown in figure 4-6 program read bus (PRDB) 2-3 program-address generation (diagram) 5-2 protocol, bus, in emulator system E-4...
  • Page 582 registers (continued) mapped to data page 0 4-8 mapped to I/O space ’C203/C204 4-24 ’C209 11-9 accessing 4-25 quick reference A-1 to A-14 status registers ST0 and ST1 3-15 timer control register (TCR) ’C203/C204 8-10 ’C209 11-16 counter register (TIM) 8-12, F-23 divide-down register (TDDR) ’C203/C204 8-12 ’C209 11-16...
  • Page 583 SDTR (synchronous serial port transmit and receive register) 9-5 using to access FIFO buffers 9-15 serial ports See also synchronous serial port; asynchronous serial port available on TMS320C2xx devices 2-12 introduction 2-12 reset conditions 5-34 serial-scan emulation capability 2-13 SETBRK bit 10-8 SETC instruction 7-155...
  • Page 584 status registers ST0 and ST1 addresses and reset values A-2 bits 3-15 clear control bit (CLRC instruction) 7-62 introduction 3-15 load (LST instruction) 7-87 load data page pointer (LDP instruction) 7-83 modify auxiliary register pointer (MAR instruc- tion) 7-111 quick reference A-5 set control bit (SETC instruction) 7-155 set product shift mode (SPM instruction) 7-167 store (SST instruction) 7-172...
  • Page 585 Index synchronous serial port (continued) troubleshooting bits for testing the port 9-27 error conditions burst mode 9-29 continuous mode 9-29 underflow in transmitter burst mode 9-29 continuous mode 9-29 synchronous serial port registers control register (SSPCR) description 9-8 quick reference A-12 FIFO buffers detecting data in receive FIFO buffer (RFNE bit) 9-9...
  • Page 586 timer control register (TCR) 8-10 to 8-12 ’C209 11-15 quick reference A-9 timer counter register (TIM) 8-12, F-23 to F-26 timer period register (PRD) 8-12, F-23 to F-26 timing calculations E-7 to E-9, E-18 to E-26 TINT bit ’C203/C204 in interrupt flag register (IFR) 5-22 in interrupt mask register (IMR) 5-23 ’C209 in interrupt flag register (IFR) 11-12...
  • Page 587 Index TSS bit ’C203/C204 8-12 ’C209 11-16 TX pin 10-4 TXM bit 9-11 TXRXINT bit in interrupt flag register (IFR) 5-21 in interrupt mask register (IMR) 5-23 TXRXINT interrupt flag bit 5-21 mask bit in IMR 5-23 priority 5-16 vector location 5-16 unconditional instructions unconditional branch 5-8 unconditional call 5-8...