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Texas Instruments TMS320C6454 Product Preview

Fixed-point digital signal processor
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1 TMS320C6454 Fixed-Point Digital Signal Processor

1.1 Features

High-Performance Fixed-Point DSP (C6454)
– 1.39-, 1.17-, and 1-ns Instruction Cycle Time
– 720-MHz, 850-MHz, and 1-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 8000 MIPS/MMACS (16-Bits)
– Commercial Temperature [0°C to 90°C]
TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling
TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
– 256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 8M-Bit (1048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– 256K-Bit (32K-Byte) L2 ROM
– Time Stamp Counter
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM and ZBT
SRAM)
– Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)
– 32M-Byte Total Addressable External
Memory Space
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
32-Bit DDR2 Memory Controller (DDR2-533
SDRAM)
EDMA3 Controller (64 Independent Channels)
32-/16-Bit Host-Port Interface (HPI)
32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
One Inter-Integrated Circuit (I
Two McBSPs
10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
– 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
16 General-Purpose I/O (GPIO) Pins
System PLL and PLL Controller
Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
697-Pin Ball Grid Array (BGA) Package
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch
0.09- m/7-Level Cu Metal Process (CMOS)
3.3-/1.8-/1.5-V I/Os, 1.25-/1.2-V Internal
Pin-Compatible with the TMS320C6455
Fixed-Point Digital Signal Processor
Copyright © 2006–2006, Texas Instruments Incorporated
TMS320C6454
2
C) Bus

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  • Page 1: Tms320C6454 Fixed-Point Digital Signal Processor

    All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Fixed-Point Digital Signal Processor SPRS311A –...

  • Page 2: Ztz/Gtz Bga Package (Bottom View)

    Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 1.1.1 ZTZ/GTZ BGA Package (Bottom View) The TMS320C6454 devices are designed for a package temperature range of 0°C to +90°C (commercial temperature range). ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls.
  • Page 3 The C6454 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor...

  • Page 4: Functional Block Diagram

    D. The PLL2 controller also generates clocks for the EMAC. E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. TMS320C6454 Fixed-Point Digital Signal Processor L1P Memory Controller (Memory Protect/Bandwidth Mgmt)

  • Page 5: Table Of Contents

    TMS320C6454 Fixed-Point Digital Signal Processor Features 1.1.1 ZTZ/GTZ BGA Package (Bottom View) Description Functional Block Diagram Device Overview Device Characteristics CPU (DSP Core) Description Memory Map Summary Boot Sequence Pin Assignments Signal Groups Description Terminal Functions Development Device Configuration...

  • Page 6: Device Characteristics

    (1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

  • Page 7: Cpu (Dsp Core) Description

    Submit Documentation Feedback Figure 2-12) Figure 2-1. The two general-purpose register files (A and B) each contain TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C6454 TMX320C6454ZTZ7, TMX320C6454ZTZ8,...
  • Page 8 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Other new features include: SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining.
  • Page 9 32 MSB ST2a 32 LSB ST2b long src even dst odd dst src2 src1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Even register register file A file A (A0, A2, (A1, A3, A4...A30)

  • Page 10: Memory Map Summary

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 2.3 Memory Map Summary Table 2-2 shows the memory map address ranges of the C6454 device. The external memory configuration register address ranges in the C6454 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
  • Page 11 C000 0000 - C07F FFFF 256M - 8M C080 0000 - CFFF FFFF D000 0000 - D07F FFFF 256M - 8M D080 0000 - DFFF FFFF 256M E000 0000 - EFFF FFFF 256M F000 0000 - FFFF FFFF TMS320C6454 Device Overview...

  • Page 12: Boot Sequence

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 2.4 Boot Sequence The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset.

  • Page 13: 2Nd-Level Bootloaders

    TI offers a few 2nd-level bootloaders, such as an EMAC bootloader, which can be loaded using the Master I2C boot. Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Device Overview...

  • Page 14: Pin Assignments

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 2.5 Pin Assignments 2.5.1 Pin Map Figure 2-2 through Figure 2-5 FSX0 CLKS GP[5] DD33 DR1/ GP[4] FSR0 GP[8] FSX1/ DX1/ CLKR0 GP[7] GP[6] GP[11] GP[9] CLKR1/...

  • Page 15: Submit Documentation Feedback

    RSV75 RSV54 RSV50 RSV73 RSV17 RSV74 RSV63 DD33 DD33 DD33 DD33 DD33 DD33 DD33 DD33 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 AED5 AED6 AED20 DD33 AED14 AED2 AED18 DD33 AED3 AED9 AED16 AED1...
  • Page 16 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DD18 DD18 RSV19 DD18 DD18 DEODT0 DEA4 DLL2 DEA8 DEA5 DEA0 DED19 DEA9 DEA6 DEA1 DED18 DEA10 DEA7 DEA2 DED16 DEA11 DEODT1 DEA3 DED17 Figure 2-4. C6454 Pin Map (Bottom View) [Quadrant C]...
  • Page 17 DD15 RSV25 DED15 DSDDQM1 DED8 DSDDQ RSV24 DED12 DD15 DD18 GATE1 DSDDQ RSV21 DED13 GATE0 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 RSV05 RSV04 DD18 DD18 DD18 DD18 DD18 DSDDQS0 RSV18 DCE0 DD18 DD18...

  • Page 18: Signal Groups Description

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 2.6 Signal Groups Description CLKIN1 SYSCLK4/GP[1] PLLV1 CLKIN2 PLLV2 TRST EMU0 EMU1 EMU14 EMU15 EMU16 EMU17 EMU18 A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
  • Page 19 Device Configuration section of this document. Submit Documentation Feedback Timer 1 Timers (64-Bit) GPIO General-Purpose Input/Output 0 (GPIO) Port Figure 2-7. Timers/GPIO Peripheral Signals TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 TOUTL0 Timer 0 TINPL0 GP[7]...
  • Page 20 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 AED[63:0] ACE5 ACE4 ACE3 ACE2 AEA[19:0] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 ABA[1:0] DED[31:0] DCE0 DEA[13:0] DSDDQM3 DSDDQM2 DSDDQM1 DSDDQM0 A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6454 device.
  • Page 21 Register Select Control Half-Word Select McBSP1 McBSP0 Transmit Transmit Receive Receive Clock Clock McBSPs (Multichannel Buffered Serial Ports) TMS320C6454 SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME CLKX0 FSX0 CLKR0 FSR0 Device Overview...
  • Page 22 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 MTXD[7:2], MTXD[1:0]/RMTXD[1:0] RGTXD[3:0] MRXD[7:2], MRXD[1:0]/RMRXD[1:0] RGRXD[3:0] MRXER/RMRXER, MRXDV, MCRS/RMCRSDV, MTXEN/RMTXEN RGTXCTL, RGRXCTL MTCLK/RMREFCLK, MRCLK, GMTCLK RGTXC, RGRXC, RGREFCLK A. RGMII signals are mutually exclusive to all other EMAC signals.
  • Page 23 Device Configuration section of this document. Submit Documentation Feedback Data/Address Clock Command Byte Enable Control Arbitration Error PCI Interface Figure 2-11. PCI Peripheral Signals TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HHWIL/PCLK PIDSEL HCNTL1/PDEVSEL HINT/PFRAME PINTA/GP[14] HAS/PPAR PRST/GP[13] HRDY/PIRDY...

  • Page 24: Terminal Functions

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 2.7 Terminal Functions The terminal functions table numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information...
  • Page 25 PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z)[default] PCI command/byte enable 3 (I/O/Z). By default, this pin has no function. PCI initialization device select (I). By default, this pin has no function. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...
  • Page 26 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME PTRDY I/O/Z HD31/AD31 HD30/AD30 HD29/AD29 HD28/AD28 HD27/AD27 HD26/AD26 HD25/AD25 HD24/AD24 I/O/Z HD23/AD23 HD22/AD22 HD21/AD21 HD20/AD20 HD19/AD19 HD18/AD18 HD17/AD17 HD16/AD16...
  • Page 27 If r_enable = 0, then the ASADS/ASRE signal functions as the ASADS signal. – If r_enable = 1, then the ASADS/ASRE signal functions as the ASRE signal. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Device Overview...
  • Page 28 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME AEA19/BOOTMODE3 AEA18/BOOTMODE2 AEA17/BOOTMODE1 AEA16/BOOTMODE0 AEA15/AECLKIN_SEL AEA14/HPI_WIDTH AEA13/LENDIAN AEA12 AEA11 Device Overview IPD/IPU EMIFA (64-BIT) - ADDRESS EMIFA external address (word address) (O/Z)
  • Page 29 DEVSTAT register. These values can be used by software routines for boot operations. AEA3: For proper C6454 device operation, the AEA3 pin must be pulled down to V with a 1-k resistor at device reset. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Device Overview...
  • Page 30 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME AED63 AED62 AED61 AED60 AED59 AED58 AED57 AED56 AED55 AED54 AED53 AED52 AED51 AED50 AED49 AED48 AED47 AED46 AED45...
  • Page 31 DSP die. DDR2 Memory Controller data strobe gate [3:0] For hookup of these signals, please refer to the Implementing DDR2 PCB Layout on a TMS320C6454 Hardware Design Application Report (literature number SPRAAA9). DDR2 Memory Controller byte-enable controls Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory.
  • Page 32 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME DSDDQS3 I/O/Z DSDDQS2 I/O/Z DSDDQS1 I/O/Z DSDDQS0 I/O/Z DSDDQS3 I/O/Z DSDDQS2 I/O/Z DSDDQS1 I/O/Z DSDDQS0 I/O/Z DDR2 MEMORY CONTROLLER (32-BIT) - ADDRESS...
  • Page 33 INTER-INTEGRATED CIRCUIT (I2C) I2C clock. When the I2C module is used, use an external pullup resistor. I2C data. When I2C is used, ensure there is an external pullup resistor. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...
  • Page 34 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0) CLKS MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
  • Page 35 However, connecting these pins directly to ground will prevent boundary-scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, see Section 7.3.4. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Section 3, Device Configuration.
  • Page 36 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME RSV12 RSV13 RSV14 RSV15 RSV16 Device Overview IPD/IPU Reserved. This pin must be connected to the 1.8-V I/O supply (DV 200- resistor for proper device operation.
  • Page 37 Reserved. This pin must be connected to the 1.8-V I/O supply (DV resistor for proper device operation. Reserved. This pin must be connected directly to ground for proper device operation. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION...
  • Page 38 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME RSV34 RSV35 RSV63 AD20 RSV64 AC15 RSV65 AC17 RSV66 AD16 RSV67 RSV68 RSV69 RSV70 RSV71 RSV72 AE17 RSV73 AE19...
  • Page 39 RGMII pins of the EMAC. To preserve boundary-scan functionality on the RGMII pins, see 1.8-V I/O supply voltage (DDR2 Memory Controller) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION...
  • Page 40 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME DD33 AA23 AB24 AC11 AC13 AC19 AC21 AC23 AC29 Device Overview IPD/IPU 3.3-V I/O supply voltage www.ti.com DESCRIPTION Submit Documentation Feedback...
  • Page 41 AG23 AH14 AH16 AH24 AJ15 AJ25 AJ29 Submit Documentation Feedback Table 2-3. Terminal Functions (continued) IPD/IPU 3.3-V I/O supply voltage 1.2-V core supply voltage TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Device Overview...
  • Page 42 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME Device Overview IPD/IPU 1.2-V core supply voltage GROUND PINS Ground pins www.ti.com DESCRIPTION Submit Documentation Feedback...
  • Page 43 SIGNAL TYPE NAME Submit Documentation Feedback Table 2-3. Terminal Functions (continued) IPD/IPU Ground pins TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Device Overview...
  • Page 44 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME Device Overview IPD/IPU Ground pins www.ti.com DESCRIPTION Submit Documentation Feedback...
  • Page 45 SIGNAL TYPE NAME AA24 AB23 AC10 AC12 AC14 AC16 AC18 Submit Documentation Feedback Table 2-3. Terminal Functions (continued) IPD/IPU Ground pins TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DESCRIPTION Device Overview...
  • Page 46 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE NAME AC20 AC22 AC24 AC28 AD13 AD15 AD17 AD19 AD21 AD23 AE16 AE18 AE20 AE22 AE24 AF19 AF21 AG13 AG16...

  • Page 47: Development

    Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
  • Page 48 TMS320C64x+™ DSP generation member. For device part numbers and further ordering information for TMS320C6454 in the ZTZ/GTZ package type, see the TI website ( www.ti.com) or contact your TI sales representative.
  • Page 49 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When configured as a dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other. Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Device Overview...

  • Page 50: Device Configuration

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 3 Device Configuration On the C6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset.
  • Page 51 The value of these pins is latched to the Device Status Register following device reset and is used by the on-chip bootloader for some boot modes. For more information on the boot modes, see Section 2.4, Boot Sequence. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table using a 1-k Device Configuration 3-3.

  • Page 52: Peripheral Configuration At Device Reset

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ PCI_EN ABA0 ABA1 3.2 Peripheral Configuration at Device Reset Some C6454 peripherals share the same pins (internally multiplexed) and are mutually exclusive.

  • Page 53: Peripheral Selection After Device Reset

    10/100 EMAC/MDIO with MII Interface [default] 10/100 EMAC/MDIO with RMII Interface 10/100/1000 EMAC/MDIO with GMII Interface 10/100/1000 EMAC/MDIO with RGMII Interface Table 3-4. Peripheral States DESCRIPTION TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 32-BIT PCI (66-/33-MHz) AUTO-INIT...
  • Page 54 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Following device reset, all peripherals that are not in the static powerdown state are in the disabled state by default. Peripherals used for boot such as HPI and PCI are enabled automatically following a device reset.

  • Page 55: Device State Control Registers

    Table 3-5. Device State Control Registers ACRONYM PERLOCK PERCFG0 PERSTAT0 PERSTAT1 EMACCFG PERCFG1 EMUBUFPD TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME Reserved Peripheral Lock Register Peripheral Configuration Register 0 Reserved Reserved Peripheral Status Register 0...

  • Page 56: Peripheral Lock Register Description

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 3.4.1 Peripheral Lock Register Description When written with correct 32-bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles.

  • Page 57: Peripheral Configuration Register 0 Description

    Submit Documentation Feedback NOTE Reserved R/W-0 PCICTL Reserved R/W-0 R/W-0 I2CCTL Reserved R/W-0 R/W-0 EMACCTL R/W-0 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HPICTL Reserved McBSP1CTL R/W-0 R/W-0 R/W-0 GPIOCTL Reserved TIMER0CTL R/W-0 R/W-0...
  • Page 58 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Field Value Description I2CCTL Mode control for I2C Set I2C to disabled mode Set I2C to enabled mode Reserved Reserved.

  • Page 59: Peripheral Configuration Register 1 Description

    EMIFA 8-bit ROM boot is used (BOOTMODE[3:0] = 0100b). Set EMIFA to disabled Set EMIFA to enabled Submit Documentation Feedback Reserved R-0x00 Reserved R-0x00 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DDR2CTL EMIFACTL R/W-0 R/W-0 Device Configuration...

  • Page 60: Peripheral Status Registers Description

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 3.4.4 Peripheral Status Registers Description The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6454 peripherals. Reserved McBSP0STAT GPIOSTAT TIMER1STAT EMACSTAT LEGEND: R = Read only; -n = value after reset Figure 3-6.
  • Page 61 EMAC/MDIO is in the enabled state EMAC/MDIO is in the static powerdown state EMAC/MDIO is in the enable in progress state Others Reserved Reserved Reserved Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Device Configuration...
  • Page 62 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 LEGEND: R = Read only; -n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions...

  • Page 63: Emac Configuration Register (Emaccfg) Description

    RMII logic reset is asserted. 17:0 Reserved Reserved. Writes to this register must keep this bit as 0. Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Reserved R/W-0 RMII_RST R/W-1 Reserved R/W-0 TMS320C6454 Reserved R/W-0 Device Configuration...

  • Page 64: Emulator Buffer Powerdown Register (Emubufpd) Description

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2]. These buffers can be powered down if the device trace feature is not needed.

  • Page 65: Device Status Register Description

    SYSCLK4 pin function of the SYSCLK4/GP[1] pin enabled Submit Documentation Feedback Table 3-13. Reserved R-0000 0000 PCI_EN CFGGP2 Reserved PCI_EEAI AECLKINSEL BOOTMODE3 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 CFGGP1 CFGGP0 Reserved MAC_SEL1 MAC_SEL0 Reserved BOOTMODE2 BOOTMODE1 BOOTMODE0...
  • Page 66 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Field Value Description MCBSP1_EN McBSP1 Enable (MCBSP1_EN) status bit Shows the status of which function is enabled on the McBSP1/GPIO muxed pins.

  • Page 67: Jtag Id (Jtagid) Register Description

    Part Number (16-Bit) value. C6454 value: 0000 0000 1000 1010b. Manufacturer (11-Bit) value. C6454 value: 0000 0010 111b. LSB. This bit is read as a "1" for C6454. TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Section 2.4, Boot Sequence.
  • Page 68 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. For the device configuration pins (listed in it is strongly recommended that an external pullup/pulldown resistor be implemented.

  • Page 69: Configuration Examples

    AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK4 pin function) AEA[3] = 0, (do not oppose IPD) AEA[2:0] (CFGGP[2:0]) = 000, (default) TIMERS + EMAC (MII) + MDIO) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 AED[63:0] AECLKIN, AARDY, AHOLD...
  • Page 70 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HD[31:0] HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 GP[15:12,2,1] CLKIN1, PLLV1 SYSCLK4 CLKR1, FSR1, DR1, CLKS1, DX1, FSX1, CLKX1 CLKR0, FSR0, DR0, CLKS0, DX0, FSX0, CLKX0...

  • Page 71: System Interconnect

    128-bit interface so that they can connect to the data SCR. Note that some peripherals can be accessed through the data SCR and also through the configuration SCR. Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Section 4.2).

  • Page 72: Data Switch Fabric Connections

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4.2 Data Switch Fabric Connections Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK2 frequency.
  • Page 73 Events Data SCR (SYSCLK2) 128-bit (SYSCLK2) (SYSCLK3) (SYSCLK3) Bridge Bridge 128 (SYSCLK2) (SYSCLK2) (SYSCLK2) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 32 (SYSCLK2) Bridge (SYSCLK3) 32 (SYSCLK3) McBSPs 32 (SYSCLK3) DDR2 (SYSCLK2) Bridge Memory...

  • Page 74: Configuration Switch Fabric

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 McBSPs CONFIGURATION SCR EMAC 4.3 Configuration Switch Fabric Figure 4-2 shows the connection between the C64x+ Megamodule and the configuration switched central resource (SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral registers.
  • Page 75 Figure 4-2. C64x+ Megamodule - SCR Connection Submit Documentation Feedback CFG SCR 32-bit (SYSCLK3) (SYSCLK2) Bridge 32 (SYSCLK2) 32 (SYSCLK2) 32 (SYSCLK2) (SYSCLK2) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (SYSCLK3) GPIO (SYSCLK3) McBSPs (SYSCLK3) (SYSCLK3) (SYSCLK3) Timers...

  • Page 76: Priority Allocation

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4.4 Priority Allocation On the C6454 device, each of the masters (excluding the C64x+ Megamodule) are assigned a priority via the Priority Allocation Register (PRI_ALLOC), see masters in the system are vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.

  • Page 77: C64X+ Megamodule

    TMS320C64x+ Megamodule Reference Guide (literature number SPRU871). 5.1 Memory Architecture The TMS320C6454 device contains a 1048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The L1P memory configuration for the C6454 device is as follows: Region 0 size is 0K bytes (disabled).
  • Page 78 Figure 5-2 Figure 5-3 show the available SRAM/cache configurations for L1P and L1D, respectively. L1P mode bits SRAM SRAM cache Figure 5-2. TMS320C6454 L1P Memory Configurations L1D mode bits SRAM SRAM 2-way cache Figure 5-3. TMS320C6454 L1D Memory Configurations C64x+ Megamodule...
  • Page 79 SRAM SRAM 4-way Figure 5-4. TMS320C6454 L2 Memory Configurations For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (literature number SPRU862). All memory on the C6454 has a unique location in the memory map (see Summary).

  • Page 80: Memory Protection

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 5.2 Memory Protection Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 16 pages of L2 (64KB each).

  • Page 81: Submit Documentation Feedback

    Section 7.6, Reset Controller. Submit Documentation Feedback NOTE Table 5-2. Megamodule Reset (Global or Local) GLOBAL RESET TYPE MEGAMODULE RESET TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 LOCAL MEGAMODULE RESET C64x+ Megamodule...

  • Page 82: Sprs311A – April 2006 – Revised December

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 5.6 Megamodule Revision The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in...

  • Page 83: Submit Documentation Feedback

    Interrupt Multiplexor Register 3 Reserved AEGMUX0 Advanced Event Generator Mux Register 0 AEGMUX1 Advanced Event Generator Mux Register 1 Reserved INTXSTAT Interrupt Exception Status Register TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME C64x+ Megamodule...

  • Page 84: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE 0180 0184 0180 0188 0180 0188 - 0180 01BC 0180 01C0 0180 01C4 - 0180 FFFF Table 5-5. Megamodule Powerdown Control Registers...

  • Page 85: Submit Documentation Feedback

    Controls EMIFA CE2 Range A200 0000 - A2FF FFFF MAR163 Controls EMIFA CE2 Range A300 0000 - A3FF FFFF MAR164 Controls EMIFA CE2 Range A400 0000 - A4FF FFFF TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME C64x+ Megamodule...

  • Page 86: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE 0184 8294 0184 8298 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4...

  • Page 87: Submit Documentation Feedback

    L2 memory protection page attribute register 0 L2MPPA1 L2 memory protection page attribute register 1 L2MPPA2 L2 memory protection page attribute register 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME REGISTER NAME...

  • Page 88: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE 0184 A20C 0184 A210 0184 A214 0184 A218 0184 A21C 0184 A220 0184 A224 0184 A228...

  • Page 89: Submit Documentation Feedback

    Reserved PERCFG1 Peripheral Configuration Register 1 Reserved EMUBUFPD Emulator Buffer Powerdown Register Reserved TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME REGISTER NAME COMMENTS Read-only. Provides status of the user's device configuration on reset.

  • Page 90: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) Supply voltage range: PLLV1, PLLV2 Input voltage (VI) range: 3.3-V pins (except PCI-capable pins)

  • Page 91: Submit Documentation Feedback

    SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 3.3 V pins (except PCI-capable and I2C pins) PCI-capable pins -0.5 I2C pins RGMII pins -0.3 DDR2 memory controller pins -0.3 (DC) TMS320C6454 MAX UNIT 0.3DV DD33 0.3DV DD33 - 0.1 REFHSTL - 0.125 REFSSTL °C Device Operating Conditions...

  • Page 92: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) PARAMETER 3.3-V pins (except PCI-capable and I2C pins) High-level PCI-capable pins...

  • Page 93: Submit Documentation Feedback

    = 3.3 V, DD33 = 1.8 V, DD18 PLLV1 = PLLV2 = AV DLL1 = 1.8 V, DLL2 CPU frequency = 720 MHz TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 13.4 1.57 1.30 1.18 0.54 0.53 0.52...

  • Page 94: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information 3.5 nH 4.0 pF 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.

  • Page 95: Submit Documentation Feedback

    External device access time DSP hold time requirement DSP setup time requirement Data route delay AECLKOUT AECLKOUT C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-1 Figure 7-4).

  • Page 96: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V manner. 7.3 Power Supplies 7.3.1 Power-Supply Sequencing TI recommends the power-supply sequence shown in...

  • Page 97: Submit Documentation Feedback

    ) via a 200- resistor. ) via a 200- resistor. DD18 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 , DV , RSV13, and RSV14...

  • Page 98: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.4 Enhanced Direct Memory Access (EDMA3) Controller The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe...

  • Page 99: Submit Documentation Feedback

    GPIO event 5 GPINT6 GPIO event 6 GPINT7 GPIO event 7 GPINT8 GPIO event 8 GPINT9 GPIO event 9 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 EVENT DESCRIPTION...

  • Page 100: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-3. C6454 EDMA3 Channel Synchronization Events (continued) EDMA BINARY CHANNEL 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 7.4.3 EDMA3 Peripheral Register Description(s) Table 7-4.

  • Page 101: Submit Documentation Feedback

    DMA Queue Number Register 2 DMAQNUM3 DMA Queue Number Register 3 Reserved QDMAQNUM QDMA Queue Number Register Reserved QUEPRI Queue Priority Register Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME...

  • Page 102: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 0300 02A0 0304 02A0 0308 02A0 030C 02A0 0310 02A0 0314 02A0 0318 02A0 031C 02A0 0320...

  • Page 103: Submit Documentation Feedback

    Event Queue 3 Entry Register 12 Q3E13 Event Queue 3 Entry Register 13 Q3E14 Event Queue 3 Entry Register 14 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME...

  • Page 104: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 04FC 02A0 0500 - 02A0 051C 02A0 0520 - 02A0 05FC 02A0 0600 02A0 0604 02A0 0608...

  • Page 105: Submit Documentation Feedback

    Parameter Set 4 Parameter Set 5 Parameter Set 6 Parameter Set 7 Parameter Set 8 Parameter Set 9 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME REGISTER NAME...

  • Page 106: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-5. EDMA3 Parameter RAM (continued) HEX ADDRESS RANGE 02A0 47E0 - 02A0 47FF 02A0 4800 - 02A0 481F 02A0 4820 - 02A0 483F 02A0 5FC0 - 02A0 5FDF 02A0 5FE0 - 02A0 5FFF Table 7-6.

  • Page 107: Submit Documentation Feedback

    SASRCBREF Source Active Source Address B-Reference Register SADSTBREF Source Active Destination Address B-Reference Register Reserved DFCNTRLD Destination FIFO Set Count Reload C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 108: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE 02A2 8284 02A2 8288 02A2 828C - 02A2 82FC 02A2 8300 02A2 8304 02A2 8308 02A2 830C...

  • Page 109: Submit Documentation Feedback

    Destination FIFO Destination Address Register 3 DFBIDX3 Destination FIFO BIDX Register 3 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 110: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE 02A3 8000 02A3 8004 02A3 8008 - 02A3 80FC 02A3 8100 02A3 8104 - 02A3 811C 02A3 8120...

  • Page 111: Submit Documentation Feedback

    Destination FIFO Destination Address Register 3 DFBIDX3 Destination FIFO BIDX Register 3 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 112: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6454 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs, the CPU exception input, or the advanced emulation logic.

  • Page 113: Submit Documentation Feedback

    L1P DMA memory protection fault L1D_CMPA L1D CPU memory protection fault L1D_DMPA L1D DMA memory protection fault L2_CMPA L2 CPU memory protection fault C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 INTERRUPT SOURCE...

  • Page 114: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-10. C6454 DSP Interrupts (continued) EVENT NUMBER INTERRUPT EVENT IDMA_CMPA IDMA_BUSERR C64x+ Peripheral Information and Electrical Specifications L2_DMPA L2 DMA memory protection fault IDMA CPU memory protection fault IDMA bus error interrupt www.ti.com...

  • Page 115: Submit Documentation Feedback

    (1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Submit Documentation Feedback Fixed-Point Digital Signal Processor Figure 7-6. NMI Interrupt Timing C64x+ Peripheral Information and Electrical Specifications TMS320C6454 SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (see Figure 7-6)

  • Page 116: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.6 Reset Controller The reset controller detects the different type of resets supported on the C6454 device and manages the distribution of those resets throughout the device.

  • Page 117: Submit Documentation Feedback

    10 cycles of their respective system reference clocks. After the pause the system clocks are restarted at their default divide-by settings. Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 NOTE C64x+ Peripheral Information and Electrical Specifications TMS320C6454...

  • Page 118: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.4, Boot Sequence). The POR pin should be held inactive (high) throughout the Warm Reset sequence.

  • Page 119: Submit Documentation Feedback

    Power-on Reset was not the last reset to occur. Power-on Reset was the last reset to occur. Submit Documentation Feedback Table 7-13. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 SRST Rsvd WRST...

  • Page 120: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.6.7 Reset Electrical Data/Timing If a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.

  • Page 121: Submit Documentation Feedback

    Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Power Supplies Stable High-Z High PLL2 Unlocked Clock Valid PLL2 Unlocked Figure 7-8. Power-Up Timing C64x+ Peripheral Information and Electrical Specifications TMS320C6454 PLL2 Locked Clock Valid w(POR)

  • Page 122: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 CLKIN1 CLKIN2 (A)(B) RESET RESETSTAT Boot and Device Configuration Pins RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see Section 7.6, Reset Controller.

  • Page 123: Submit Documentation Feedback

    7-10. The 1.8-V supply of the EMI filter must be from the 7.7.4, PLL1 Controller Input and Output Clock Electrical Data/Timing. CAUTION module described C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 . TI requires EMI filter manufacturer DD18 TMS320C645x...

  • Page 124: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 TMS320C6454 DSP +1.8 V PLLV1 EMI Filter 560 pF 0.1 mF CLKIN1 AECLKIN (External EMIF Clock Input) DIVIDER D2 and DIVIDER D3 are always enabled. CLKIN1 is a 3.3-V signal.

  • Page 125: Submit Documentation Feedback

    PLL1 reset time value, see Submit Documentation Feedback Table Table 7-16. PLL1 Clock Frequency Ranges Table 7-17. C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7-16. 66.6 33.3 66.6...

  • Page 126: Submit Documentation Feedback

    7.7.2 PLL1 Controller Memory Map The memory map of the PLL1 controller is shown in are accessible on the TMS320C6454. Other addresses in the PLL1 controller memory map should not be modified. Table 7-18. PLL1 Controller Registers (Including Reset Controller)

  • Page 127: Submit Documentation Feedback

    Not all of the registers documented in the TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRUE56) are supported on the TMS320C6454. Only those registers documented in this section are supported. Furthermore, only the bits within the registers described here are supported.

  • Page 128: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.2 PLL Multiplier Control Register The PLL multiplier control register (PLLM) is shown in register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits (RATIO) in the PLL controller pre-divider register (PREDIV).

  • Page 129: Submit Documentation Feedback

    3h-1Fh Reserved, do not use. Submit Documentation Feedback Figure 7-13 Reserved Reserved 3. Divide frequency by 3. C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 and described in Table 7-21. RATIO...

  • Page 130: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.4 PLL Controller Divider 4 Register The PLL controller divider 4 register (PLLDIV4) is shown in Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the system.

  • Page 131: Submit Documentation Feedback

    ÷5 to ÷8. Divide frequency by 5 to divide frequency by 8. 8h-1Fh Reserved, do not use. Submit Documentation Feedback Figure 7-15 Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 and described in Table 7-23. RATIO...

  • Page 132: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.6 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in LEGEND: R/W = Read/Write;...

  • Page 133: Submit Documentation Feedback

    GO operation is not in progress. SYSCLK divide ratios are not being changed. GO operation is in progress. SYSCLK divide ratios are being changed. Submit Documentation Feedback Table 7-25. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 GOSTAT...

  • Page 134: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.8 PLL Controller Clock Align Control Register The PLL controller clock align control register (ALNCTL) is shown in Table 7-26. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-18.

  • Page 135: Submit Documentation Feedback

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Submit Documentation Feedback Table 7-27. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 SYS5 SYS4 Reserved...

  • Page 136: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.10 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 7-20 and described in Reserved LEGEND: R = Read only;...

  • Page 137: Submit Documentation Feedback

    (1) (2) [CPU/8 - CPU/12] (see Figure PARAMETER MAX and V Figure 7-22. SYSCLK4 Timing C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (1) (2) (3) (see Figure 7-21) -720...

  • Page 138: Submit Documentation Feedback

    7-23. The 1.8-V supply for the EMI filter must be from the same . TI requires EMI filter manufacturer Murata, DD18 Section 7.8.4, PLL2 Controller Input Clock Electrical Data/Timing. CAUTION module described TMS320C6454 DSP PLLREF PLLOUT PLL2 PLLM PLL2 Controller Figure 7-23. PLL2 Block Diagram www.ti.com...

  • Page 139: Submit Documentation Feedback

    Table 7-31. Also, when EMAC is enabled with RGMII or GMII, CLKIN2 Table 7-31. PLL2 Clock Frequency Ranges Section C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 12.5 26.7 7.6, Reset Controller ) and is locked by...

  • Page 140: Submit Documentation Feedback

    SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.2 PLL2 Controller Memory Map The memory map of the PLL2 controller is shown in are accessible on the TMS320C6454. Other addresses in the PLL2 controller memory map should not be modified. HEX ADDRESS RANGE...

  • Page 141: Submit Documentation Feedback

    ÷5. Divide frequency by 5. Others Reserved Submit Documentation Feedback Figure 7-24 Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 and described in Table 7-33. RATIO R/W-1...

  • Page 142: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.2 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in LEGEND: R/W = Read/Write;...

  • Page 143: Submit Documentation Feedback

    RATIO bit in PLLDIV1. Submit Documentation Feedback Table 7-35. Reserved Reserved Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-18 and described in GOSTAT ALN1 R/W-1...

  • Page 144: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.5 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will only change the divide ratio SYSCLK1 if SYS1 in DCHANGE is 1.

  • Page 145: Submit Documentation Feedback

    Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. SYS1ON SYSCLK1 on status. SYSCLK1 is gated. SYSCLK1 is on. Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-38. Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 SYS1ON...

  • Page 146: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing Table 7-39. Timing Requirements for CLKIN2 Cycle time, CLKIN2 c(CLKIN2) Pulse duration, CLKIN2 high w(CLKIN2H) Pulse duration, CLKIN2 low w(CLKIN2L)

  • Page 147: Submit Documentation Feedback

    For the C6454 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met.

  • Page 148: Submit Documentation Feedback

    7800 0100 - 7FFF FFFF 7.9.3 DDR2 Memory Controller Electrical Data/Timing The Implementing DDR2 PCB Layout on the TMS320C6454 application report (literature number SPRAAA7) specifies a complete DDR2 interface solution for the C6454 as well as a list of compatible DDR2 devices.

  • Page 149: Submit Documentation Feedback

    3 ensures that the previous write was done. Submit Documentation Feedback Fixed-Point Digital Signal Processor Table 2-3, Terminal Functions). C64x+ Peripheral Information and Electrical Specifications TMS320C6454 SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 150: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.10.2 EMIFA Peripheral Register Description(s) HEX ADDRESS RANGE 7000 0000 7000 0004 7000 0008 7000 000C - 7000 001C 7000 0020 7000 0024 - 7000 004C 7000 0050 - 7000 007C...

  • Page 151: Submit Documentation Feedback

    (4) This timing only applies when AECLKIN is used for EMIFA. AECLKIN Submit Documentation Feedback MAX and V Figure 7-31. AECLKIN Timing for EMIFA C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (1) (2) (see Figure...

  • Page 152: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the Cycle time, AECLKOUT c(EKO) Pulse duration, AECLKOUT high w(EKOH) Pulse duration, AECLKOUT low w(EKOL) Transition time, AECLKOUT...

  • Page 153: Submit Documentation Feedback

    (see Figure 7-33 PARAMETER Strobe = 4 Byte Enables Address DEASSERTED C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-34) -720 -850 -1000 RS * E – 1.5 RS * E –...

  • Page 154: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Setup = 1 AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE AAWE/ASWE AR/W AARDY A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory accesses.

  • Page 155: Submit Documentation Feedback

    (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1). Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (see Figure 7-36) (see Figure 7-36–Figure PARAMETER C64x+ Peripheral Information and Electrical Specifications TMS320C6454 -720 -850 UNIT -1000 7-38) -720 -850 UNIT -1000...

  • Page 156: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE AAOE/ASOE AAWE/ASWE A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn): −Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency −Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle read latency...

  • Page 157: Submit Documentation Feedback

    B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses. Figure 7-38. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Write Latency = C64x+ Peripheral Information and Electrical Specifications TMS320C6454...

  • Page 158: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.10.4 HOLD/HOLDA Timing Table 7-48. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module Hold time, HOLD low after HOLDA low h(HOLDAL-HOLDL) (1) E = the EMIF input clock (ECLKIN) period in ns for EMIFA.

  • Page 159: Submit Documentation Feedback

    ABUSREQ Submit Documentation Feedback for EMIFA Module (see Figure PARAMETER Figure 7-40. BUSREQ Timing for EMIFA C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7-40) -720 -850 -1000 UNIT...

  • Page 160: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.11 I2C Peripheral The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I way of an I C-bus.

  • Page 161: Submit Documentation Feedback

    Buffer Receive Receive I2CDRR Buffer Receive I2CRSR Shift Figure 7-41. I2C Module Block Diagram C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Control I2COAR Address Slave I2CSAR Address I2CMDR...

  • Page 162: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.11.2 I2C Peripheral Register Description(s) HEX ADDRESS RANGE 02B0 4000 02B0 4004 02B0 4008 02B0 400C 02B0 4010 02B0 4014 02B0 4018 02B0 401C 02B0 4020 02B0 4024...

  • Page 163: Submit Documentation Feedback

    C-bus™ system, but the requirement t su(SDA-SCLH) max + t = 1000 + 250 = 1250 ns su(SDA-SCLH) of the SCL signal) to bridge the IHmin ] of the SCL signal. w(SCLL) C64x+ Peripheral Information and Electrical Specifications TMS320C6454 UNIT 250 ns must then...

  • Page 164: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Stop Start Table 7-53. Switching Characteristics for I2C Timings PARAMETER Cycle time, SCL c(SCL) Delay time, SCL high to SDA low (for a d(SCLH-SDAL) repeated START condition)

  • Page 165: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Stop Start Repeated Stop Start Figure 7-43. I2C Transmit Timings Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications...

  • Page 166: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information The C6454 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32). The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.

  • Page 167: Submit Documentation Feedback

    SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (1) (2) (see valid before HAS low valid after HAS low valid before HSTROBE low valid after HSTROBE low C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Table 7-56 through Figure 7-51) -720 -850 UNIT...

  • Page 168: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-56. Switching Characteristics for Host-Port Interface Cycles Delay time, HSTROBE low to d(HSTBL-HDV) DSP data valid Disable time, HD high-impedance from HSTROBE high dis(HSTBH-HDV) Enable time, HD driven from HSTROBE low...

  • Page 169: Submit Documentation Feedback

    HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-44. HPI16 Read Timing (HAS Not Used, Tied High) Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 170: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.

  • Page 171: Submit Documentation Feedback

    HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-46. HPI16 Write Timing (HAS Not Used, Tied High) Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 172: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.

  • Page 173: Submit Documentation Feedback

    HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-48. HPI32 Read Timing (HAS Not Used, Tied High) Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 174: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HAS (input) HCNTL[1:0] (input) HR/W (input) HSTROBE (input) HCS (input) HD[31:0] (output) HRDY (output) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

  • Page 175: Submit Documentation Feedback

    HPI peripheral, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969). Figure 7-50. HPI32 Write Timing (HAS Not Used, Tied High) Submit Documentation Feedback Fixed-Point Digital Signal Processor C64x+ Peripheral Information and Electrical Specifications TMS320C6454 SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...
  • Page 176 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 HAS (input) HCNTL[1:0] (input) HR/W (input) HSTROBE (input) HCS (input) HD[31:0] (input) HRDY (output) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

  • Page 177: Submit Documentation Feedback

    For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel Buffered Serial Port ( McBSP) Reference Guide (literature number SPRU580, rev. E or later). Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C64x+ Peripheral Information and Electrical Specifications TMS320C6454...

  • Page 178: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.13.1 McBSP Device-Specific Information The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

  • Page 179: Submit Documentation Feedback

    Register 3 Partition G/H McBSP1 Enhanced Transmit Channel Enable XCERE31 Register 3 Partition G/H Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 COMMENTS The CPU and EDMA controller can only read this register;...

  • Page 180: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.13.2 McBSP Electrical Data/Timing 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP Cycle time, CLKR/X c(CKRX) Pulse duration, CLKR/X high or CLKR/X low...

  • Page 181: Submit Documentation Feedback

    CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 -720 -850 -1000 C – 1 C + 1 –2.1...

  • Page 182: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 CLKS CLKR FSR (int) FSR (ext) CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) Bit 0 Parameter No. 13 applies to the first data bit only when XDATDLY The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

  • Page 183: Submit Documentation Feedback

    L – 2 L + 3 –2 L – 2 L + 3 Bit(n-1) (n-2) (n-3) Bit(n-1) (n-2) C64x+ Peripheral Information and Electrical Specifications TMS320C6454 (1) (2) -720 -850 -1000 UNIT SLAVE 2 – 18P 5 + 36P 7-54) -720...

  • Page 184: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Setup time, DR valid before CLKX high su(DRV-CKXH) Hold time, DR valid after CLKX high h(CKXH-DRV) (1) P = 1/CPU clock frequency in ns.

  • Page 185: Submit Documentation Feedback

    7-56) MASTER T – 2 H – 2 H – 2 Bit(n-1) Bit(n-1) C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 -720 -850 -1000 MASTER SLAVE 2 – 18P...

  • Page 186: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Setup time, DR valid before CLKX high su(DRV-CKXH) Hold time, DR valid after CLKX high h(CKXH-DRV) (1) P = 1/CPU clock frequency in ns.

  • Page 187: Submit Documentation Feedback

    Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DMA Memory Configuration Bus Transfer Controller Peripheral Bus EMAC Control Module EMAC Module MDIO Module MDIO Bus Ethernet Bus C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Figure 7-58. The...

  • Page 188: Submit Documentation Feedback

    7.14.1 EMAC Device-Specific Information Interface Modes The EMAC module on the TMS320C6454 supports four interface modes: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are defined in the IEEE 802.3-2002 standard.

  • Page 189: Submit Documentation Feedback

    MCOL GMTCLK MRCLK MRCLK MTCLK/REFCLK MTCLK GMDIO MDIO GMDCLK MDCLK C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 RMII GMII (MAC_SEL = (MAC_SEL = 01b) 10b) RMRXD0 MRXD0 RMRXD1...

  • Page 190: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see Section 7.8, PLL2 and PLL2 Controller.

  • Page 191: Submit Documentation Feedback

    Receive Channel 2 Free Buffer Count Register RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 192: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE 02C8 0154 02C8 0158 02C8 015C 02C8 0160 02C8 0164 02C8 0168 02C8 016C 02C8 0170...

  • Page 193: Submit Documentation Feedback

    (Total number of jabber frames received) Receive Undersized Frames Register RXUNDERSIZED (Total number of undersized frames received) RXFRAGMENTS Receive Frame Fragments Register C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006...

  • Page 194: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE 02C8 0228 02C8 022C 02C8 0230 02C8 0234 02C8 0238 TXBCASTFRAMES 02C8 023C TXMCASTFRAMES 02C8 0240 TXPAUSEFRAMES 02C8 0244...

  • Page 195: Submit Documentation Feedback

    Figure 7-60. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation] Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 1000 Mbps (GMII Only) 100 Mbps C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Figure 7-59) -720 -850 -1000 UNIT 100 Mbps...

  • Page 196: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Cycle time, GMTCLK c(GMTCLK) Pulse duration, GMTCLK high w(GMTCLKH) Pulse duration, GMTCLK low w(GMTCLKL) Transition time, GMTCLK...

  • Page 197: Submit Documentation Feedback

    Submit Documentation Feedback Transmit 10/100 Mbit/s (see Figure PARAMETER 1000 Mbit/s (see Figure PARAMETER C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7-63) -720 -850 -1000 100/10 Mbps 7-64) -720...

  • Page 198: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency should be 50 MHz ±50 PPM with a duty cycle between 35% and 65%, inclusive.

  • Page 199: Submit Documentation Feedback

    MCRSDV, MRXER (Inputs) Figure 7-67. EMAC Receive Interface Timing [RMII Operation] Submit Documentation Feedback Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 (see Figure 7-67) -720 -850 UNIT -1000...

  • Page 200: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock. This should only be used by an external device if it does not expect a valid clock during device reset.

  • Page 201: Submit Documentation Feedback

    100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps 10 Mbps 100 Mbps 1000 Mbps C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (see Figure -720 -850 -1000 (A)(B)

  • Page 202: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Setup time, transmit selected signals valid before TXC (at DSP) high/low su(TXD-TXCH) Hold time, transmit selected signals valid after TXC (at DSP) high/low h(TXCH-TXD) (1) For RGMII, transmit selected signals include: TXD[3:0] and TXCTL.

  • Page 203: Submit Documentation Feedback

    MDIO User PHY Select Register 0 USERACCESS1 MDIO User Access Register 1 USERPHYSEL1 MDIO User PHY Select Register 1 Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-58. REGISTER NAME...

  • Page 204: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.4.3 MDIO Electrical Data/Timing Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Cycle time, MDCLK c(MDCLK) Pulse duration, MDCLK high w(MDCLK) Pulse duration, MDCLK low w(MDCLK)

  • Page 205: Submit Documentation Feedback

    Timer 1 Control Register TGCR1 Timer 1 Global Control Register WDTCR1 Timer 1 Watchdog Timer Control Register Reserved Reserved Reserved C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 COMMENTS REGISTER NAME COMMENTS...

  • Page 206: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.15.3 Timers Electrical Data/Timing Table 7-94. Timing Requirements for Timer Inputs Pulse duration, TINPLx high w(TINPH) Pulse duration, TINPLx low w(TINPL) (1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

  • Page 207: Submit Documentation Feedback

    3, Device Configuration. Table 7-96. Default Values for PCI Configuration Registers REGISTER NOTE C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-96 shows the registers which can DEFAULT...

  • Page 208: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.16.2 PCI Peripheral Register Description(s) PCI HOST ACCESS HEX ADDRESS OFFSET 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 - 0x2B 0x2C 0x30 0x34...

  • Page 209: Submit Documentation Feedback

    PCI Base Address Register 5 Mirror Register Reserved PCIMCFGDAT PCI Master Configuration/IO Access Data Register PCIMCFGADR PCI Master Configuration/IO Access Address Register C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 DSP ACCESS REGISTER NAME...

  • Page 210: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers (continued) DSP ACCESS HEX ADDRESS RANGE 02C0 0308 PCIMCFGCMD 02C0 030C - 02C0 030F 02C0 0310 Table 7-99. DSP-to_PCI Address Translation Registers...

  • Page 211: Submit Documentation Feedback

    PCI Master Window 10 PCI Master Window 11 PCI Master Window 12 PCI Master Window 13 PCI Master Window 14 C64x+ Peripheral Information and Electrical Specifications TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 REGISTER NAME...

  • Page 212: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-101. PCI External Memory Space (continued) HEX ADDRESS OFFSET 4780 0000 - 47FF FFFF 4800 0000 - 487F FFFF 4880 0000 - 48FF FFFF 4900 0000 - 497F FFFF...

  • Page 213: Submit Documentation Feedback

    7.16.3 PCI Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specification (version 2.3). The AC timing specifications are not reproduced here. For more information on the AC timing specifications, see section 4.2.3, Timing Specification (33 MHz timing), and section 7.6.4, Timing...

  • Page 214: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.17 General-Purpose Input/Output (GPIO) 7.17.1 GPIO Device-Specific Information On the C6454 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the PCI and McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral configuration and the C6454 device pin muxing, see 7.17.2 GPIO Peripheral Register Description(s)

  • Page 215: Submit Documentation Feedback

    Submit Documentation Feedback Fixed-Point Digital Signal Processor (1) (2) (see Figure 7-74) PARAMETER Figure 7-74. GPIO Port Timing C64x+ Peripheral Information and Electrical Specifications TMS320C6454 SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 (see Figure 7-74) -720 -850 -1000 -720...

  • Page 216: Submit Documentation Feedback

    TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.

  • Page 217: Submit Documentation Feedback

    The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 °C/W...

  • Page 218: Submit Documentation Feedback

    This data sheet revision history highlights the technical changes made to the SPRS311 device-specific data sheet to make it an SPRS311A revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6454 device, have been incorporated. Global...

  • Page 219: Submit Documentation Feedback

    3-7, Peripheral Configuration Register 0 (PERCFG0) Field Descriptions Figure 3-12, Configuration Example A, and 5-4, TMS320C6454 L2 Memory Configurations 6.1, Absolute Maximum Ratings Over Operating Case Temperature Range 6.2, Recommended Operating Conditions 6.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and...

  • Page 220: Submit Documentation Feedback

    TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Section 7.7.3 PLL1 Controller Register Descriptions: Added Values and Descriptions for RATIO bit field in Field Descriptions Deleted PLL Controller Divider Registers section Added new sections for PLL Controller Divider 4 Register and PLL Controller Divider 5 Register...

  • Page 221: Submit Documentation Feedback

    7-84, Switching Characteristics Over Recommended Operating Conditions for EMAC 7-68, RGREFCLK Timing Table 7-87 title to Switching Characteristics Over Recommended Operating Conditions for TXC - 7-96, Default Values for PCI Configuration Registers TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Revision History...

  • Page 222: Packaging Information

    www.ti.com PACKAGING INFORMATION Orderable Device Status TMS320C6454BZTZ ACTIVE TMS320C6454BZTZ7 ACTIVE TMS320C6454BZTZ8 ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.
  • Page 225 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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