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TMS320C6454
Texas Instruments TMS320C6454 Manuals
Manuals and User Guides for Texas Instruments TMS320C6454. We have
2
Texas Instruments TMS320C6454 manuals available for free PDF download: Product Preview, User Manual
Texas Instruments TMS320C6454 Product Preview (225 pages)
Fixed-Point Digital Signal Processor
Brand:
Texas Instruments
| Category:
Processor
| Size: 1.84 MB
Table of Contents
1 TMS320C6454 Fixed-Point Digital Signal Processor
1
Features
1
ZTZ/GTZ BGA Package (Bottom View)
2
Description
2
Functional Block Diagram
4
Table of Contents
5
2 Device Overview
5
Device Characteristics
6
CPU (DSP Core) Description
7
Memory Map Summary
10
Boot Sequence
12
Pin Assignments
14
Submit Documentation Feedback
15
Signal Groups Description
18
Terminal Functions
24
Development
47
3 Device Configuration
50
Device Configuration at Device Reset
50
Peripheral Configuration at Device Reset
52
Peripheral Selection after Device Reset
53
Device State Control Registers
55
Device Status Register Description
65
JTAG ID (JTAGID) Register Description
67
Pullup/Pulldown Resistors
67
Configuration Examples
69
4 System Interconnect
71
Internal Buses, Bridges, and Switch Fabrics
71
Data Switch Fabric Connections
72
Configuration Switch Fabric
74
Priority Allocation
76
5 C64X+ Megamodule
77
Memory Architecture
77
Memory Protection
80
Bandwidth Management
80
Power-Down Control
81
Megamodule Resets
81
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81
Sprs311A – April 2006 – Revised December
82
Megamodule Revision
82
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82
C64X+ Megamodule Register Description(S)
83
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83
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84
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89
6 Device Operating Conditions
90
Absolute Maximum Ratings over Operating Case Temperature Range (Unless Otherwise Noted)
90
Recommended Operating Conditions
90
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90
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91
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
92
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92
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93
7 C64X+ Peripheral Information and Electrical Specifications
94
Parameter Information
94
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94
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95
Recommended Clock and Control Signal Transition Behavior
96
Power Supplies
96
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96
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97
Enhanced Direct Memory Access (EDMA3) Controller
98
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98
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99
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100
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101
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102
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103
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108
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110
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111
Interrupts
112
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112
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113
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114
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115
Reset Controller
116
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116
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117
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118
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119
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120
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121
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122
PLL1 and PLL1 Controller
123
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123
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124
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125
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126
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127
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128
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132
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135
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136
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137
PLL2 and PLL2 Controller
138
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138
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139
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140
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141
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142
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143
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144
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145
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146
DDR2 Memory Controller
147
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147
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148
External Memory Interface a (EMIFA)
149
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149
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150
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151
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152
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153
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154
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155
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156
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159
I2C Peripheral
160
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160
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161
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162
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163
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164
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165
Host-Port Interface (HPI) Peripheral
166
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166
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167
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168
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169
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170
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171
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172
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173
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174
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175
Multichannel Buffered Serial Port (Mcbsp)
177
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177
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178
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179
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180
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181
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186
Ethernet MAC (EMAC)
187
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187
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188
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189
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190
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191
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202
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203
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204
Timers
205
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205
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206
Peripheral Component Interconnect (PCI)
207
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207
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208
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209
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210
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211
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212
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213
General-Purpose Input/Output (GPIO)
214
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214
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215
Ieee 1149.1 Jtag
216
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216
8 Mechanical Data
217
Thermal Data
217
Packaging Information
217
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217
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218
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219
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220
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221
Packaging Information
222
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Texas Instruments TMS320C6454 User Manual (50 pages)
DSP DDR2 Memory Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.36 MB
Table of Contents
Table of Contents
3
Preface
7
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
10
Device Block Diagram
10
Peripheral Architecture
11
Clock Control
11
Memory Map
11
Signal Descriptions
11
DDR2 Memory Controller Signals
12
DDR2 Memory Controller Signal Descriptions
12
Protocol Description(S)
13
DDR2 SDRAM Commands
13
Truth Table for DDR2 SDRAM Commands
13
DDR2 MRS and EMRS Command
14
Refresh Command
15
ACTV Command
16
DCAB Command
17
DEAC Command
18
DDR2 READ Command
19
Memory Width, Byte Alignment, and Endianness
20
DDR2 WRT Command
20
Addressable Memory Ranges
20
Address Mapping
21
Byte Alignment
21
Bank Configuration Register Fields for Address Mapping
21
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map
23
DDR2 Memory Controller Interface
24
DDR2 SDRAM Column, Row, and Bank Access
24
DDR2 Memory Controller FIFO Description
24
DDR2 Memory Controller FIFO Block Diagram
25
Refresh Scheduling
27
Refresh Urgency Levels
27
Self-Refresh Mode
28
2.10 Reset Considerations
28
2.11 DDR2 SDRAM Memory Initialization
28
Device and DDR2 Memory Controller Reset Relationship
28
DDR2 SDRAM Mode Register Configuration
29
DDR2 SDRAM Extended Mode Register 1 Configuration
29
2.12 Interrupt Support
30
2.13 EDMA Event Support
30
2.14 Emulation Considerations
30
Using the DDR2 Memory Controller
31
Connecting the DDR2 Memory Controller to DDR2 SDRAM
31
Connecting to Two 16-Bit DDR2 SDRAM Devices
32
Connecting to a Single 16-Bit DDR2 SDRAM Device
33
Connecting to Two 8-Bit DDR2 SDRAM Devices
34
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
35
SDCFG Configuration
35
DDR2 Memory Refresh Specification
36
SDRFC Configuration
36
SDTIM1 Configuration
36
SDTIM2 Configuration
37
DMCCTL Configuration
37
DDR2 Memory Controller Registers
38
Module ID and Revision Register (MIDR)
39
Module ID and Revision Register (MIDR) Field Descriptions
39
DDR2 Memory Controller Status Register (DMCSTAT)
40
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
40
SDRAM Configuration Register (SDCFG)
41
SDRAM Configuration Register (SDCFG) Field Descriptions
41
SDRAM Refresh Control Register (SDRFC)
43
SDRAM Refresh Control Register (SDRFC) Field Descriptions
43
SDRAM Timing 1 Register (SDTIM1)
44
SDRAM Timing 1 Register (SDTIM1) Field Descriptions
44
SDRAM Timing 2 Register (SDTIM2)
46
SDRAM Timing 2 Register (SDTIM2) Field Descriptions
46
Burst Priority Register (BPRIO)
47
Burst Priority Register (BPRIO) Field Descriptions
47
DDR2 Memory Controller Control Register (DMCCTL)
48
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
48
Revision History
49
Important Notice
50
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