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Texas Instruments MSP50C6xx Manuals
Manuals and User Guides for Texas Instruments MSP50C6xx. We have
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Texas Instruments MSP50C6xx manual available for free PDF download: User Manual
Texas Instruments MSP50C6xx User Manual (390 pages)
Mixed-Signal Processor
Brand:
Texas Instruments
| Category:
Processor
| Size: 1 MB
Table of Contents
Table of Contents
7
Read this First
3
1 Introduction to the Msp50C6Xx
15
Features of the Msp50C6Xx
16
Resistor-Trimmed Oscillator
16
Applications
17
Development Device: MSP50P614
18
Functional Description for the MSP50C614
19
Functional Block Diagram for the MSP50C614/MSP50P614
19
Oscillator and PLL Connection
21
RESET Circuit
22
MSP50C601, MSP50C604, and MSP50C605
23
2 Msp50C6Xx Architecture
25
Architecture Overview
26
Msp50C6Xx Core Processor Block Diagram
27
Computational Unit Block Diagram
28
Computation Unit
29
Multiplier
29
Signed and Unsigned Integer Representation
29
Arithmetic Logic Unit
31
Overview of the Multiplier Unit Operation
31
Overview of the Arithmetic Logic Unit
33
Overview of the Accumulators
34
Data Memory Address Unit
35
RAM Configuration
36
Data Memory Addressing Modes
37
Bit Logic Unit
38
Program Counter Unit
38
Memory Map
39
Memory Organization: RAM and ROM
39
Peripheral Communications (Ports)
40
C6Xx Memory Map (Not Drawn to Scale)
40
Summary of Msp50C614'S Peripheral Communications Ports
41
Interrupt Vectors
42
ROM Code Security
43
Interrupt Logic
46
Macro Call Vectors
46
Interrupt Initialization Sequence
49
Clock Control
50
Oscillator Options
50
PLL Performance
50
Clock Speed Control Register
52
RTO Oscillator Trim Adjustment
53
Timer Registers
55
Reduced Power Modes
57
Programmable Bits Needed to Control Reduced Power Modes
60
Status of Circuitry When in Reduced Power Modes (Refer to Table 2-3)
61
How to Wake up from Reduced Power Modes (Refer to Table 2-3 and Table 2-4)
62
Destination of Program Counter on Wake-Up under Various Conditions
63
Execution Timing
64
Instruction Execution and Timing
64
3 Peripheral Functions
65
I/O
66
General-Purpose I/O Ports
66
Dedicated Input Port F
68
Dedicated Output Port G
69
Branch on D Port
70
Internal and External Interrupts
71
Interrupts
72
DAC Control and Data Registers
73
Digital-To-Analog Converter (DAC)
73
Pulse-Density Modulation Rate
73
PDM Clock Divider
75
Comparator
79
Relationship between Comparator/Interrupt Activity and the TIMER1 Control
80
Interrupt/General Control Register
82
Hardware Initialization States
84
State of the Status Register (17 Bit) after RESET Low-To-High
86
(Bits 5 through 16 Are Left Uninitialized)
86
Assembly Language Instructions
87
Introduction
88
System Registers
88
Data Pointer Register (DP)
88
Multiplier Register (MR)
88
Program Counter (PC)
88
Shift Value Register (SV)
88
Top of Stack, (TOS)
89
Top of Stack (TOS) Register Operation
89
System Registers
89
Accumulators (AC0–AC31)
90
Product High Register (PH)
90
Product Low Register (PL)
90
Accumulator Pointers (AP0–AP3)
91
Indirect Register (R0–R7)
91
String Register (STR)
92
Status Register (STAT)
92
Status Register (STAT)
93
Instruction Syntax and Addressing Modes
94
MSP50P614/MSP50C614 Instruction Syntax
94
Addressing Modes
95
Addressing Mode Encoding
95
Addressing Mode Bits and {Adrs} Field Description
96
Rx Bit Description
96
Auto Increment and Auto Decrement Modes
97
MSP50P614/MSP50C614 Addressing Modes Summary
97
Flag Addressing Field {Flagadrs} for Certain Flag Instructions (Class 8A)
98
Immediate Addressing
99
Initial Processor State for the Examples before Execution of Instruction
99
Direct Addressing
100
Indirect Addressing Syntax
101
Relative Addressing
102
Relative Flag Addressing
105
Tag/Flag Bits
106
Instruction Classification
108
Instruction Classification
109
Symbols and Explanation
108
Classes and Opcode Definition
111
Class 1 Instruction Encoding
112
Class 1A Instruction Description
112
Class 1B Instruction Description
113
Class 2 Instructions: Accumulator and Constant Reference
114
Class 2 Instruction Encoding
115
Class 2A Instruction Description
115
Class 3 Instruction: Accumulator Reference
116
Class 2B Instruction Description
116
Class 3 Instruction Encoding
117
Class 4 Instructions: Address Register and Memory Reference
120
Class 3 Instruction Description
120
Class 4A Instruction Encoding
120
Class 4A Instruction Description
121
Class 4B Instruction Description
121
Class 4C Instruction Description
121
Class 4D Instruction Description
121
Class 5 Instructions: Memory Reference
122
Class 5 Instruction Description
122
Class 6 Instructions: Port and Memory Reference
124
Class 5 Instruction Encoding
122
Class 6A Instruction Description
124
Class 7 Instructions: Program Control
125
Class 6A Instruction Encoding
124
Class 6B Instruction Description
125
Class 7 Instruction Encoding and Description
126
Class 8 Instructions: Logic and Bit
127
Class 8A Instruction Encoding
127
Class 9 Instructions: Miscellaneous
128
Class 8A Instruction Description
128
Class 8B Instruction Description
128
Class 9A Instruction Description
129
Class 9A Instruction Encoding
129
Class 9B Instruction Description
129
Class 9C Instruction Description
130
Class 9D Instruction Description
130
Bit, Byte, Word and String Addressing
130
Data Memory Organization and Addressing
131
Data Memory Address and Data Relationship
132
Data Memory Example
133
MSP50P614/MSP50C614 Computational Modes
135
MSP50P614/MSP50C614 Computational Modes
136
Hardware Loop Instructions
139
Hardware Loops in MSP50P614/MSP50C614
140
Initial Processor State for String Instructions
141
String Instructions
141
Lookup Instructions
143
FIR Filter Structure
145
Input/Output Instructions
145
Special Filter Instructions
145
Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps
153
Filter Instruction and Circular Buffering for N+1 Tap Filter
154
Conditionals
155
Legend
156
Addressing Mode Bits and Adrs Field Description
159
Auto Increment and Decrement
159
Flag Addressing Syntax and Bits
159
Individual Instruction Descriptions
160
Names for CC
174
Interrupt Disable
193
Interrupt Enable
194
Return from Interrupt
195
Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set
218
Shift Left
248
Instruction Set Encoding
275
Instruction Set Summary
284
5 Code Development Tools
297
Introduction
298
Pin IDC Connector (Top View Looking at the Board)
299
Categories of Msp50Cxx Development Tools
300
Msp50C6Xx Development Tools Guidelines
300
Tools Definitions
301
Documentation
304
Msp50C6Xx Code Development Tools
304
System Requirements
304
Hardware Tools Setup
305
Hardware Tools Setup
306
Assembler
307
Assembler Directives
307
C– – Compiler
312
Foreword
312
External References
313
Variable Types
313
C– – Directives
314
Include Files
315
Function Prototypes and Declarations
317
Initializations
317
RAM Usage
317
String Functions
318
Constant Functions
319
Implementation Details
320
Programming Example
323
Beware of Stack Corruption
353
Reported Bugs with Code Development Tool
354
Application Circuits
356
Minimum Circuit Configuration for the C614/P614 Using a
356
Minimum Circuit Configuration for the C614/P614 Using a Crystal-Referenced Oscillator
357
Initializing the Msp50C6Xx
358
File Init.asm
359
Ti-Talks Example Code
362
Ram Overlay
363
Common Problems
365
7 Customer Information
367
Mechanical Information
368
Signal and Pad Descriptions for the MSP50C614
369
Signal and Pad Descriptions for the MSP50C605
370
Signal and Pad Descriptions for the MSP50C601
371
Signal and Pad Descriptions for the MSP50C604
372
Pin QFP Mechanical Information
373
Pin QFP Mechanical Information
374
Pin, Grid Array Package for the Development Device, MSP50P614
375
Bottom View of 120-Pin PGA Package of the MSP50P614
376
Customer Information Fields in the Rom
377
Device Production Sequence
378
Speech Development Cycle
378
New Product Release Forms (Nprf)
380
Ordering Information
380
Additional Information
389
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