Device Status Register Description - Texas Instruments SM320C6455-EP Data Manual

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3.5

Device Status Register Description

The device status register depicts the device configuration selected upon device reset. Once set, these
bits will remain set until a device reset. For the actual register bit names and their associated bit field
descriptions, see
Note that enabling or disabling peripherals through the Peripheral Configuration Registers (PERCFG0 and
PERCFG1) does not affect the DEVSTAT register. To determine the status of peripherals following writes
to the PERCFG0 and PERCFG1 registers, read the Peripherals Status Registers (PERSTAT0 and
PERSTAT1).
31
23 22
Reserved EMIFA_EN
R-0 R-0
15 14
SYSCLKOUT_
MCBSP1_EN
EN
R-0 R-0
7 6
UTOPIA_EN LENDIAN
R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -x = value after reset
Note: The default values of the fields in the DEVSTAT register are latched from device configuration pins, as described in
Device Configuration at Device Reset. The default values shown here correspond to the setting dictated by the internal pullup or pulldown
resistor.
Table 3-13. Device Status Register (DEVSTAT) Field Descriptions
Bit Field
31:23 Reserved
22 EMIFA_EN
21 DDR2_EN
20 PCI_EN
19:17 CFGGP[2:0]
16 Reserved
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Figure 3-10 and Table 3-13.
21
DDR2_EN PCI_EN
R-0 R-0
13
PCI66 Reserved
R-0 R-0
5
HPI_WIDTH AECLKINSEL
R-0 R-0
Figure 3-10. Device Status Register (DEVSTAT) - 0x02A8 0000
Value Description
Reserved. Read-only, writes have no effect.
EMIFA Enable (EMIFA_EN) status bit
Shows the status of whether the EMIFA peripheral pins are enabled/disabled.
0 EMIFA peripheral pins are disabled (default)
1 EMIFA peripheral pins are enabled
DDR2 Memory Controller Enable (DDR2_EN) status bit
Shows the status of whether the DDR2 Memory Controller peripheral pins are enabled/disabled.
0 DDR2 Memory Controller peripheral pins are disabled (default)
1 DDR2 Memory Controller peripheral pins are enabled
PCI Enable (PCI_EN) status bit
Shows the status of which function is enabled on the HPI/PCI and PCI/UTOPIA multiplexed pins.
0 HPI and UTOPIA pin functions are enabled (default)
1 PCI pin functions are enabled
Used as General-Purpose inputs for configuration purposes.
These pins are latched at reset. These values can be used by S/W routines for boot operations.
Reserved. Read-only, writes have no effect.
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Reserved
R-0000 0000
20 19
CFGGP2
R-0
12 11
PCI_EEAI
R-0
4 3
BOOTMODE3 BOOTMODE2
R-0
SM320C6455-EP
18 17
CFGGP1 CFGGP0
R-0 R-0
10 9
MAC_SEL1 MAC_SEL0
R-0 R-0
2 1
BOOTMODE1
R-0 R-0
Device Configuration
24
16
Reserved
R-1
8
Reserved
R-1
0
BOOTMODE0
R-0
Section 3.1,
75