Status Register St1, Bits 7−0 - Texas Instruments TMS320C28x Reference Manual

Register Figures
Figure A−3. Status Register ST1, Bits 7−0
7 6
0 0
IDLESTAT EALLOW
R
R/W
Stack pointer alignment bit
0 Stack pointer has not been
1 aligned to even address
Stack pointer has been aligned to
even address
Loop instruction status bit
0 LOOPNZ/LOOPZ instruction done
1 LOOPNZ/LOOPZ instruction in
progress
Emulation access enable bit
0 Access to emulation registers disabled
1 Access to emulation registers enabled
IDLE status flag bit
0 IDLE instruction done
1 IDLE instruction in progress
†
These reserved bits are always 0s and are not affected by writes.
‡
The VMAP bit depends on the level of the VMAP input signal at reset. If the VMAP signal is low, the VMAP bit is 0 after reset;
if the VMAP signal is high, the VMAP bit is 1 after reset. For C28x devices that do not pin out the VMAP signal, the signal is tied
high internal to the device.
Note: For more details about ST1, see section 2.4 on page 2-34.
5 4
É É É É
0 0
É É É É
LOOP SPA
É É É É
R
R/W
Vector map bit
0
1
3 2
É É É É É
X ‡ 0
É É É É É
VMAP PAGE0
É É É É É
R/W
R/W
Interrupt enable mask bit
0 Maskable interrupts globally enabled
1 Maskable interrupts globally disabled
Debug enable mask bit
0 Debug events enabled
1 Debug events disabled
PAGE0 addressing configuration bit
0 PAGE0 stack addressing mode
1 PAGE0 direct addressing mode
Interrupt vectors mapped to program-
memory addresses 00 0000
Interrupt vectors mapped to program-
memory addresses 3F FFC0
1 0
1 1
DBGM INTM
R/W
R/W
−00 003F
16 16
−3F FFFF
16 16