Table 7−4. Start Address and DMA Registers
Address
Name
00 0838
ADDRL
16
00 0839
ADDRH
16
00 083E
DMA_CNTRL
16
00 083F
DMA_ID
16
Access
Description
R/W
Start address register (lower 16 bits)
15:0
R/W
Word counter/start address register (upper 6 bits)
15:8
7:6
5:0
R/W
DMA control register
15:14
13
12
11
10
9
8:6
5:4
3:2
1:0
R
DMA ID register
15:14
13:12
11:0
Lower 16 bits of start address
Word counter. When using this to stop the data
logging transfer, set the counter to 256 − n,
where n is the number of 32-bit words to
transfer. Otherwise set the counter to 0.
Reserved. Set to 0.
Upper 6 bits of start address
Set to 0
Set to 1
Set to 1
Give higher priority to:
0: CPU (nonpreemptive mode)
1: Data logging (preemptive mode)
Allow data logging during time-critical ISR?
0: No
1: Yes
Allow data logging while DBGM = 1?
0: No (polite accesses)
1: Yes (rude accesses)
Set to 1
0: EMU0/EMU1 using TCK
1: EMU0/EMU1 using FCK/2
2: JTAG signals
3: Reserved
Method for ending data logging session:
0: Use the count register to stop data logging
1: Use an end address to stop data logging
Data logging control/status:
0: Release resource from data logging operation
1: Claim resource for data logging operation
2: Enable resource for data logging operation
3: Data logging operation is complete. Bits 14:10
are corrupted when this occurs.
Resource control:
0: Resource is free
1: Application owns resource
2: Debugger owns resource
Set to 3.
Set to 1.
Emulation Features
Data Logging
7-25
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