Configuration - Texas Instruments TMS320C6000 Manual

SPRA545A
Table 1. MC68360 to HPI Pin Connections (Continued)
HPI Pin MC68360 Pin
- AVEC='0'
HRDY DSACK1
HINT IRQx
DS (data strobe) of the MC68360 is not used in this interface because the MC68360 asserts DS
only after it latches a DSACK low. However, the HPI of the C6000 does not assert HRDY
(DSACK1) until after DS is asserted. Because of this timing conflict, HDS1 and HDS2 of the
TMS320C6000 HPI are tied logic low and high, respectively, to enable data strobe at all times.
The HPI must keep DSACKx asserted until it detects the negation of AS or DS (whichever it
detects first). The C6000 must negate DSACKx within approximately one clock period after
sampling negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be
prematurely detected for the next bus cycle. This is avoided by using an OR combination of the
HRDY and CSx signals.
HBE1 and HBE2 of the HPI are tied low to enable host access to both lower and upper bytes of
the halfword during a write in the TMS320C6201/6701. Although the MC68360 has byte write
enable signals WE1 and WE0, they are not used in this interface because of timing issues. The
HPI expects control signals, including HBE1 and HBE0, to be ready before data strobe (which is
HCS in this case) is asserted. However, MC68360 asserts chip-select and write-enable signals
at the same time. Therefore, WE1 and WE0 cannot be used.
The auto-vector (AVEC) signal is used to terminate interrupt acknowledge cycles, indicating that
the QUICC should internally generate a vector (auto-vector) number to locate an interrupt
handler routine. AVEC is ignored during all other bus cycles.
1.1

Configuration

The QUICC is comprised of three modules:
•
CPU32+ core
•
System integration module (SIM60)
•
Communication processor module (CPM)
The memory controller is a sub-block of the SIM60 that is responsible for up to eight
general-purpose chip-select lines. The general-purpose chip-selects are available on lines
CS0-CS7. CS0 also functions as the global (boot) chip-select for accessing the boot EPROM.
The SIM60 supports a glue-less interface to HPI.
4 TMS320C6000 Host Port to MC68360 Interface
The Auto Vector input function is selected in normal operation.
The SPS bits in the MC68360 option registers need to be set to indicate that DSACK1
is generated externally by HPI. (See the
User can select interrupt level (IRQ1 to IRQ7). Priority level 7 interrupt is a special case.
Level 7 interrupts are non-maskable interrupts (NMI). IRQ7 is a level-sensitive input and
must remain low until the second instruction processing module (CPU32+) returns an
interrupt acknowledge cycle for interrupt 7. (See the
Communications Controller User's Manual
Comments
MC68360
User's Manual for details)
MC68360 Quad Integrated
for a detailed description.)