Pll And Pll Controller - Texas Instruments TMS320C6712D User Manual

TMS320C6712D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PLL and PLL controller

The TMS320C6712D includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and
four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different
parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other
peripherals). Figure 8 illustrates the PLL, the PLL controller, and the clock generator logic.
+3.3 V
C1 C2
EMI filter
10 µF 0.1 µF
For Use
in System
† Dividers D1 and D2 must never be disabled. Never write a "0" to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV DD .
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
46
PLLHV
CLKMODE0
CLKIN
DIVIDER D0
1
0
Reserved
OSCDIV1
CLKOUT3
/1, /2,
..., /32
ENA
OD1EN (OSCDIV1.[15])
ECLKIN
(EMIF Clock Input)
C6712D DSP
Figure 8. PLL and Clock Generator Logic
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
PLLOUT
PLLREF
/1, /2,
PLL
..., /32
1
x4 to x25
ENA ENA ENA
0
D1EN (PLLDIV1.[15])
D0EN (PLLDIV0.[15])
D2EN (PLLDIV2.[15])
D3EN (PLLDIV3.[15])
PLLEN (PLL_CSR.[0])
DIVIDER D1 †
/1, /2, SYSCLK1
..., /32
(DSP Core)
ENA
DIVIDER D2 †
/1, /2,
SYSCLK2
..., /32
(Peripherals)
ENA
DIVIDER D3
/1, /2,
..., /32
SYSCLK3
ENA
EKSRC Bit
1 0
(DEVCFG.[4])
EMIF
ECLKOUT